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| author | Shaunak Saha <shaunak.saha@intel.com> | 2018-03-21 07:39:40 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-03-25 17:55:53 +0000 |
| commit | cf1ba95fa4daffecaa9d1764163c28e7acf24c6c (patch) | |
| tree | ebfdf11e376f8a17b4445cf730cf867cf10d2889 | |
| parent | d18f42ab6f5e166084da42f237690b5836854456 (diff) | |
| download | coreboot-cf1ba95fa4daffecaa9d1764163c28e7acf24c6c.tar.xz | |
mb/glkrvp: Set PNP config to PNP_PERF_POWER
This patch sets the PNP config value to PNP_PERF_POWER.
The config values for soc can be found in chip.h
TEST = Built and booted glkrvp, verified warm and cold
reboot and suspend resume.
Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 5a544300c0..f9ed3cfbff 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -98,6 +98,8 @@ chip soc/intel/apollolake # 0x08000000 - 128MiB register "PrmrrSize" = "128 * MiB" + register "pnp_settings" = "PNP_PERF_POWER" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |