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authorMarc Jones <marc.jones@se-eng.com>2015-06-09 21:18:38 -0600
committerMarc Jones <marc.jones@se-eng.com>2015-06-13 18:09:20 +0200
commitd862121fbe6285be2f91a0c09058a22a775c0d19 (patch)
tree4ef78f4c720e49a81303f81ccfa957d2fcd64bf1
parentf2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1 (diff)
downloadcoreboot-d862121fbe6285be2f91a0c09058a22a775c0d19.tar.xz
google/auron: Add mainboard
Add the Google Auron Broadwell Reference Mainboard. It is based on the Google Peppy mainboard. It was merged from the following chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10500 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/auron/Kconfig39
-rw-r--r--src/mainboard/google/auron/Kconfig.name4
-rw-r--r--src/mainboard/google/auron/Makefile.inc33
-rw-r--r--src/mainboard/google/auron/acpi/chromeos.asl6
-rw-r--r--src/mainboard/google/auron/acpi/ec.asl4
-rw-r--r--src/mainboard/google/auron/acpi/mainboard.asl238
-rw-r--r--src/mainboard/google/auron/acpi/superio.asl4
-rw-r--r--src/mainboard/google/auron/acpi/thermal.asl41
-rw-r--r--src/mainboard/google/auron/acpi/video.asl43
-rw-r--r--src/mainboard/google/auron/acpi_tables.c42
-rw-r--r--src/mainboard/google/auron/board_info.txt4
-rw-r--r--src/mainboard/google/auron/chromeos.c36
-rw-r--r--src/mainboard/google/auron/devicetree.cb166
-rw-r--r--src/mainboard/google/auron/dsdt.asl20
-rw-r--r--src/mainboard/google/auron/ec.c6
-rw-r--r--src/mainboard/google/auron/ec.h5
-rw-r--r--src/mainboard/google/auron/fadt.c113
-rw-r--r--src/mainboard/google/auron/gma.c276
-rw-r--r--src/mainboard/google/auron/gpio.h202
-rw-r--r--src/mainboard/google/auron/hda_verb.h (renamed from src/mainboard/google/auron/hda_verb.c)95
-rw-r--r--src/mainboard/google/auron/i915io.c143
-rw-r--r--src/mainboard/google/auron/mainboard.c33
-rw-r--r--src/mainboard/google/auron/mainboard.h25
-rw-r--r--src/mainboard/google/auron/onboard.h6
-rw-r--r--src/mainboard/google/auron/pei_data.c67
-rw-r--r--src/mainboard/google/auron/romstage.c177
-rw-r--r--src/mainboard/google/auron/smihandler.c56
-rw-r--r--src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex (renamed from src/mainboard/google/auron/Elpida_EDJ4216EFBG.spd.hex)0
-rw-r--r--src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex (renamed from src/mainboard/google/auron/Hynix_HMT425S6AFR6A.spd.hex)0
-rw-r--r--src/mainboard/google/auron/spd/Makefile.inc54
-rw-r--r--src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex (renamed from src/mainboard/google/auron/Micron_4KTF25664HZ.spd.hex)0
-rw-r--r--src/mainboard/google/auron/spd/empty.spd.hex16
-rw-r--r--src/mainboard/google/auron/spd/spd.c139
-rw-r--r--src/mainboard/google/auron/spd/spd.h43
-rw-r--r--src/mainboard/google/auron/thermal.h11
35 files changed, 1014 insertions, 1133 deletions
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 2c1560aad4..779e6b37b6 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -1,12 +1,8 @@
-if BOARD_GOOGLE_PEPPY
+if BOARD_GOOGLE_AURON
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select SYSTEM_TYPE_LAPTOP
- select CPU_INTEL_HASWELL
- select NORTHBRIDGE_INTEL_HASWELL
- select SOUTHBRIDGE_INTEL_LYNXPOINT
- select INTEL_LYNXPOINT_LP
+ select SOC_INTEL_BROADWELL
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
select EC_SOFTWARE_SYNC
@@ -19,24 +15,32 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select INTEL_DP
- select INTEL_DDI
+ select CACHE_ROM
+ select MARK_GRAPHICS_MEM_WRCOMB
+ select CHROMEOS_RAMOOPS_DYNAMIC
select INTEL_INT15
+ select LID_SWITCH
select CHROMEOS_VBNV_CMOS
+config VBOOT_RAMSTAGE_INDEX
+ hex
+ default 0x2
+
+config VBOOT_REFCODE_INDEX
+ hex
+ default 0x3
+
config MAINBOARD_DIR
string
- default google/peppy
+ default google/auron
config MAINBOARD_PART_NUMBER
string
- default "Peppy"
+ default "Auron"
-config MMCONF_BASE_ADDRESS
- hex
- default 0xf0000000
+config IRQ_SLOT_COUNT
+ int
+ default 18
config MAX_CPUS
int
@@ -54,4 +58,9 @@ config HAVE_ME_BIN
bool
default n
+
+config MAINBOARD_FAMILY
+ string
+ depends on GENERATE_SMBIOS_TABLES
+ default "Google_Auron"
endif
diff --git a/src/mainboard/google/auron/Kconfig.name b/src/mainboard/google/auron/Kconfig.name
index 8049a54360..e996627af7 100644
--- a/src/mainboard/google/auron/Kconfig.name
+++ b/src/mainboard/google/auron/Kconfig.name
@@ -1,2 +1,2 @@
-config BOARD_GOOGLE_PEPPY
- bool "Peppy"
+config BOARD_GOOGLE_AURON
+ bool "Auron"
diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc
index 97eaccae6a..68ba413362 100644
--- a/src/mainboard/google/auron/Makefile.inc
+++ b/src/mainboard/google/auron/Makefile.inc
@@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
-## Copyright (C) 2012 Google Inc.
+## Copyright (C) 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -17,36 +17,15 @@
## Foundation, Inc.
##
+subdirs-y += spd
+
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += chromeos.c
ramstage-y += chromeos.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-## DIMM SPD for on-board memory
-SPD_BIN = $(obj)/spd.bin
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1
-SPD_SOURCES += Elpida_EDJ4216EFBG # 2: 4GB / CH0 + CH1
-SPD_SOURCES += Micron_4KTF25664HZ # 3: Reserved / place holder
-SPD_SOURCES += Micron_4KTF25664HZ # 4: 2GB / CH0 + CH1
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 + CH1
-SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-
-# Include spd rom data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do printf $$(printf '\%o' 0x$$c); \
- done; \
- done > $@
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
+romstage-y += pei_data.c
+ramstage-y += pei_data.c
diff --git a/src/mainboard/google/auron/acpi/chromeos.asl b/src/mainboard/google/auron/acpi/chromeos.asl
index 9db5509ad3..d9297178d4 100644
--- a/src/mainboard/google/auron/acpi/chromeos.asl
+++ b/src/mainboard/google/auron/acpi/chromeos.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,6 +18,6 @@
*/
Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
- Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
+ Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button
+ Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
})
diff --git a/src/mainboard/google/auron/acpi/ec.asl b/src/mainboard/google/auron/acpi/ec.asl
index d8b62867fd..712da33f42 100644
--- a/src/mainboard/google/auron/acpi/ec.asl
+++ b/src/mainboard/google/auron/acpi/ec.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
*/
/* mainboard configuration */
-#include <mainboard/google/peppy/ec.h>
+#include "ec.h"
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl
index 3406e8c5b5..8461a9d459 100644
--- a/src/mainboard/google/auron/acpi/mainboard.asl
+++ b/src/mainboard/google/auron/acpi/mainboard.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -18,7 +18,7 @@
* Foundation, Inc.
*/
-#include <mainboard/google/peppy/onboard.h>
+#include <mainboard/google/auron/onboard.h>
Scope (\_SB)
{
@@ -30,68 +30,190 @@ Scope (\_SB)
Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
Return (\LIDS)
}
+
+
+ // There is no GPIO for LID, the EC pulses WAKE# pin instead.
+ // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
+ Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
}
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
+}
- Device (TPAD)
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
{
- Name (_ADR, 0x0)
- Name (_UID, 1)
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
- // Report as a Sleep Button device so Linux will
- // automatically enable it as a wake source
- Name (_HID, EisaId("PNP0C0E"))
+Scope (\_SB.PCI0.I2C0)
+{
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
+ I2cSerialBus (
+ 0x15, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
+ })
- VendorShort (ADDR)
+ Method (_STA)
{
- BOARD_TRACKPAD_I2C_ADDR
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
}
- })
+ }
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
-
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
- \_SB.PCI0.LPCB.GWAK (Local0)
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
}
- Device (TSCR)
+ Device (CTPA)
{
- Name (_ADR, 0x0)
- Name (_UID, 2)
+ Name (_HID, "CYAP0000")
+ Name (_DDN, "Cypress Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
- // Report as a Sleep Button device so Linux will
- // automatically enable it as a wake source
- Name (_HID, EisaId("PNP0C0E"))
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x67, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (CTPB)
+ {
+ Name (_HID, "CYAP0001")
+ Name (_DDN, "Cypress Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
+ I2cSerialBus (
+ 0x24, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C0", // ResourceSource
+ )
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
- BOARD_TOUCHSCREEN_IRQ
+ BOARD_TRACKPAD_IRQ
}
+ })
- VendorShort (ADDR)
+ Method (_STA)
{
- BOARD_TOUCHSCREEN_I2C_ADDR
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+Scope (\_SB.PCI0.I2C1)
+{
+ Device (ATSA)
+ {
+ Name (_HID, "ATML0001")
+ Name (_DDN, "Atmel Touchscreen")
+ Name (_UID, 5)
+ Name (_S0W, 4)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x4a, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.PCI0.I2C1", // ResourceSource
+ )
+
+ // GPIO54 (ball L3) is PIRQW: PIRQL_GSI + PIRQL - PIRQW = PIRQW_GSI
+ // 27 + 3 - 14 = 38
+ Interrupt (ResourceConsumer, Edge, ActiveLow) { 38 }
})
Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
@@ -99,10 +221,80 @@ Scope (\_SB)
Method (_DSW, 3, NotSerialized)
{
Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+ }
+ }
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+ Device (ALSI)
+ {
+ /*
+ * TODO(dlaurie): Need official HID.
+ *
+ * The current HID is created from the Intersil PNP
+ * Vendor ID "LSD" and a shortened device identifier.
+ */
+ Name (_HID, EisaId ("LSD2918"))
+ Name (_DDN, "Intersil 29018 Ambient Light Sensor")
+ Name (_UID, 6)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x44, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+
+ // On Auron/Peppy board, IRQ is hooked to GPIO 51.
+ // Based on table 5-36, this is PIRQT. Then based on
+ // table 5-12, this is IRQ #35.
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ 35
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.PCI0.RP01)
+{
+ Device (WLAN)
+ {
+ Name (_ADR, 0x00000000)
+
+ /* GPIO10 is WLAN_WAKE_L_Q */
+ Name (GPIO, 10)
+
+ Name (_PRW, Package() { GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
- \_SB.PCI0.LPCB.GWAK (Local0)
+ \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
}
}
}
diff --git a/src/mainboard/google/auron/acpi/superio.asl b/src/mainboard/google/auron/acpi/superio.asl
index 0203cad3dc..11ae2d7b6d 100644
--- a/src/mainboard/google/auron/acpi/superio.asl
+++ b/src/mainboard/google/auron/acpi/superio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
*/
/* mainboard configuration */
-#include <mainboard/google/peppy/ec.h>
+#include <mainboard/google/auron/ec.h>
#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl
index 0533048782..28394978b1 100644
--- a/src/mainboard/google/auron/acpi/thermal.asl
+++ b/src/mainboard/google/auron/acpi/thermal.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,8 @@
* Foundation, Inc.
*/
+#include <mainboard/google/auron/thermal.h>
+
// Thermal Zone
Scope (\_TZ)
@@ -61,7 +63,7 @@ Scope (\_TZ)
Return (\PPKG ())
}
- Method (_TMP, 0, Serialized)
+ Method (TCHK, 0, Serialized)
{
// Get Temperature from TIN# set in NVS
Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
@@ -94,21 +96,46 @@ Scope (\_TZ)
Return (Local0)
}
+ Method (_TMP, 0, Serialized)
+ {
+ // Get temperature from EC in deci-kelvin
+ Store (TCHK (), Local0)
+
+ // Critical temperature in deci-kelvin
+ Store (CTOK (\TCRT), Local1)
+
+ If (LGreaterEqual (Local0, Local1)) {
+ Store ("CRITICAL TEMPERATURE", Debug)
+ Store (Local0, Debug)
+
+ // Wait 1 second for EC to re-poll
+ Sleep (1000)
+
+ // Re-read temperature from EC
+ Store (TCHK (), Local0)
+
+ Store ("RE-READ TEMPERATURE", Debug)
+ Store (Local0, Debug)
+ }
+
+ Return (Local0)
+ }
+
/* CTDP Down */
Method (_AC0) {
If (LLessEqual (\FLVL, 0)) {
- Return (CTOK (\F0OF))
+ Return (CTOK (CTL_TDP_THRESHOLD_OFF))
} Else {
- Return (CTOK (\F0ON))
+ Return (CTOK (CTL_TDP_THRESHOLD_ON))
}
}
/* CTDP Nominal */
Method (_AC1) {
If (LLessEqual (\FLVL, 1)) {
- Return (CTOK (\F1OF))
+ Return (CTOK (CTL_TDP_THRESHILD_NORMAL))
} Else {
- Return (CTOK (\F1ON))
+ Return (CTOK (CTL_TDP_THRESHILD_NORMAL))
}
}
@@ -128,7 +155,7 @@ Scope (\_TZ)
Store (0, \FLVL)
/* Enable Power Limit */
- \_SB.PCI0.MCHC.CTLE (\F0PW)
+ \_SB.PCI0.MCHC.CTLE (CTL_TDP_POWER_LIMIT)
Notify (\_TZ.THRM, 0x81)
}
diff --git a/src/mainboard/google/auron/acpi/video.asl b/src/mainboard/google/auron/acpi/video.asl
new file mode 100644
index 0000000000..3ececa912b
--- /dev/null
+++ b/src/mainboard/google/auron/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c
index 47288aa7db..540fe44032 100644
--- a/src/mainboard/google/auron/acpi_tables.c
+++ b/src/mainboard/google/auron/acpi_tables.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,27 +29,16 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
#include "thermal.h"
+extern const unsigned char AmlCode[];
+
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->tmps = CTL_TDP_SENSOR_ID;
- /* Normal TDP */
- gnvs->f1of = 0;
- gnvs->f1on = 0;
-
- /* Limited TDP */
- gnvs->f0of = CTL_TDP_THRESHOLD_OFF;
- gnvs->f0on = CTL_TDP_THRESHOLD_ON;
- gnvs->f0pw = CTL_TDP_POWER_LIMIT;
-
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tmax = MAX_TEMPERATURE;
@@ -58,22 +47,13 @@ static void acpi_update_thermal_table(global_nvs_t *gnvs)
void acpi_create_gnvs(global_nvs_t *gnvs)
{
+ acpi_init_gnvs(gnvs);
+
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
- gnvs->s3u1 = 1;
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
- gnvs->s5u1 = 0;
-
- /* TPM Present */
- gnvs->tpmp = 1;
-
-
-#if CONFIG_CHROMEOS
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
acpi_update_thermal_table(gnvs);
}
@@ -87,11 +67,5 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
+ return acpi_madt_irq_overrides(current);
}
diff --git a/src/mainboard/google/auron/board_info.txt b/src/mainboard/google/auron/board_info.txt
index a802401fe2..ab5f291aa1 100644
--- a/src/mainboard/google/auron/board_info.txt
+++ b/src/mainboard/google/auron/board_info.txt
@@ -1,5 +1,5 @@
-Vendor name: Acer
-Board name: C720 Chromebook
+Vendor name: Google
+Board name: Auron Broadwell Reference Board
Category: laptop
ROM package: SOIC-8
ROM protocol: SPI
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c
index ef10c48997..a5e2aea1f4 100644
--- a/src/mainboard/google/auron/chromeos.c
+++ b/src/mainboard/google/auron/chromeos.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,16 +18,17 @@
*/
#include <string.h>
-#include <bootmode.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-
-#if CONFIG_EC_GOOGLE_CHROMEEC
-#include "ec.h"
+#include <console/console.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include <ec/google/chromeec/ec.h>
-#endif
+#include <soc/gpio.h>
+#include "ec.h"
+
+/* SPI Write protect is GPIO 16 */
+#define CROS_WP_GPIO 58
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -36,15 +37,24 @@
static int get_lid_switch(void)
{
-#if CONFIG_EC_GOOGLE_CHROMEEC
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
return !!(ec_switches & EC_SWITCH_LID_OPEN);
-#else
- return 0;
-#endif
}
+/*static void fill_lb_gpio(struct lb_gpio *gpio, int num,
+ int polarity, const char *name, int force)
+{
+ memset(gpio, 0, sizeof(*gpio));
+ gpio->port = num;
+ gpio->polarity = polarity;
+ if (force >= 0)
+ gpio->value = force;
+ else if (num >= 0)
+ gpio->value = get_gpio(num);
+ strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
+}
+*/
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio *gpio;
@@ -53,7 +63,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->count = GPIO_COUNT;
gpio = gpios->gpios;
- fill_lb_gpio(gpio++, 58, ACTIVE_HIGH, "write protect", 0);
+ fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
get_recovery_mode_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
@@ -95,5 +105,5 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
- return get_gpio(58);
+ return get_gpio(CROS_WP_GPIO);
}
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 505b39e0b9..77e71b8d3d 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -1,7 +1,4 @@
-chip northbridge/intel/haswell
- # IGD Displays
- register "gfx.ndid" = "3"
- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
@@ -24,103 +21,88 @@ chip northbridge/intel/haswell
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- device cpu_cluster 0 on
- chip cpu/intel/haswell
- device lapic 0 on end
- # Magic APIC ID to locate this chip
- device lapic 0xACAC off end
-
- register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
- register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
-
- register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
- register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
- end
- end
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
- device domain 0 on
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
- chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
+ register "sata_port_map" = "0x1"
+ register "sio_acpi_mode" = "1"
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
- register "sata_port_map" = "0x1"
+ # Force enable ASPM for PCIe Port1
+ register "pcie_port_force_aspm" = "0x01"
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
+ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013c0000"
- register "sio_acpi_mode" = "0"
- register "sio_i2c0_voltage" = "0" # 3.3V
- register "sio_i2c1_voltage" = "0" # 3.3V
+ register "s0ix_enable" = "1"
- # Force enable ASPM for PCIe Port1
- register "pcie_port_force_aspm" = "0x01"
-
- # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013c0000"
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
- device pci 13.0 off end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 on end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 on end # SMBus
- device pci 1f.6 on end # Thermal
- end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
end
end
diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index 76998ba670..1c10f80da3 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,8 +18,6 @@
* Foundation, Inc.
*/
-#define ENABLE_TPM
-
DefinitionBlock(
"dsdt.aml",
"DSDT",
@@ -30,23 +28,22 @@ DefinitionBlock(
)
{
// Some generic macros
- #include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
+ #include <soc/intel/broadwell/acpi/platform.asl>
// global NVS and variables
- #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+ #include <soc/intel/broadwell/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// CPU
- #include <cpu/intel/haswell/acpi/cpu.asl>
+ #include <soc/intel/broadwell/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
- #include <northbridge/intel/haswell/acpi/haswell.asl>
- #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ #include <soc/intel/broadwell/acpi/systemagent.asl>
+ #include <soc/intel/broadwell/acpi/pch.asl>
}
}
@@ -58,5 +55,8 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
- #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+ #include <soc/intel/broadwell/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
}
diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c
index dbe73487cd..54a42a7adb 100644
--- a/src/mainboard/google/auron/ec.c
+++ b/src/mainboard/google/auron/ec.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,6 +18,7 @@
*/
#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include <types.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
@@ -37,7 +38,8 @@ void mainboard_ec_init(void)
google_chromeec_set_smi_mask(0);
/* Clear pending events */
- while (google_chromeec_get_event() != 0);
+ while (google_chromeec_get_event() != 0)
+ ;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
diff --git a/src/mainboard/google/auron/ec.h b/src/mainboard/google/auron/ec.h
index 706993c165..8e71fdb7a8 100644
--- a/src/mainboard/google/auron/ec.h
+++ b/src/mainboard/google/auron/ec.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -33,8 +33,11 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
#define MAINBOARD_EC_SMI_EVENTS \
diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c
index bae03d6de4..237954cf3c 100644
--- a/src/mainboard/google/auron/fadt.c
+++ b/src/mainboard/google/auron/fadt.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,20 +19,16 @@
*/
#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/pch.h>
+#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
- u16 pmbase = get_pmbase();
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
- header->revision = 3;
+ header->revision = 5;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
@@ -42,114 +39,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
- fadt->sci_int = 0x9;
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0;
-
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x80;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 32;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0;
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 87;
- fadt->flush_size = 1024;
- fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x00;
- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
-
- fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 0;
- fadt->x_gpe0_blk.bit_width = 0;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = 0;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_in_fadt(fadt);
header->checksum =
acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/google/auron/gma.c b/src/mainboard/google/auron/gma.c
deleted file mode 100644
index 735ad65f9e..0000000000
--- a/src/mainboard/google/auron/gma.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <types.h>
-#include <string.h>
-#include <stdlib.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <delay.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <smbios.h>
-#include <device/pci.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <edid.h>
-#include <drivers/intel/gma/i915.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include "mainboard.h"
-
-/*
- * Here is the rough outline of how we bring up the display:
- * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
- * 2. Source determines video mode by reading DPCD receiver capability field
- * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
- * 0000Dh).
- * 3. Sink replies DPCD receiver capability field.
- * 4. Source starts EDID read thru I2C-over-AUX.
- * 5. Sink replies EDID thru I2C-over-AUX.
- * 6. Source determines link configuration, such as MAX_LINK_RATE and
- * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
- * method to use and writes DPCD link configuration field (DPCD 00100h to
- * 0010Ah) including eDP configuration set (DPCD 0010Ah).
- * 7. Source starts link training. Sink does clock recovery and equalization.
- * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
- * 9. Sink replies DPCD link status field. If main link is not stable, Source
- * repeats Step 7.
- * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
- * parameters and recovers stream clock.
- * 11. Source sends video data.
- */
-
-/* how many bytes do we need for the framebuffer?
- * Well, this gets messy. To get an exact answer, we have
- * to ask the panel, but we'd rather zero the memory
- * and set up the gtt while the panel powers up. So,
- * we take a reasonable guess, secure in the knowledge that the
- * MRC has to overestimate the number of bytes used.
- * 8 MiB is a very safe guess. There may be a better way later, but
- * fact is, the initial framebuffer is only very temporary. And taking
- * a little long is ok; this is done much faster than the AUX
- * channel is ready for IO.
- */
-#define FRAME_BUFFER_BYTES (8*MiB)
-/* how many 4096-byte pages do we need for the framebuffer?
- * There are hard ways to get this, and easy ways:
- * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
- * on this chip (and in fact every Intel graphics chip we've seen).
- */
-#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
-
-
-static int i915_init_done = 0;
-
-/* fill the palette. */
-static void palette(void)
-{
- int i;
- unsigned long color = 0;
-
- for(i = 0; i < 256; i++, color += 0x010101){
- gtt_write(_LGC_PALETTE_A + (i<<2),color);
- }
-}
-
-void mainboard_train_link(struct intel_dp *intel_dp)
-{
- u8 read_val;
- u8 link_status[DP_LINK_STATUS_SIZE];
-
- gtt_write(DP_TP_CTL(intel_dp->port),
- DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
- gtt_write(DDI_BUF_CTL_A,
- DDI_BUF_CTL_ENABLE|
- DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011);
-
- intel_dp_get_training_pattern(intel_dp, &read_val);
- intel_dp_set_training_pattern(intel_dp,
- DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE |
- DP_SYMBOL_ERROR_COUNT_BOTH);
-
- intel_dp_set_training_lane0(intel_dp,
- DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
- intel_dp_get_link_status(intel_dp, link_status);
-
- gtt_write(DP_TP_CTL(intel_dp->port),
- DP_TP_CTL_ENABLE |
- DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
-
- intel_dp_get_training_pattern(intel_dp, &read_val);
- intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 |
- DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
- intel_dp_get_link_status(intel_dp, link_status);
- intel_dp_get_lane_align_status(intel_dp, &read_val);
- intel_dp_get_training_pattern(intel_dp, &read_val);
- intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE |
- DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
-}
-
-/* This variable controls whether the test_gfx function below puts up
- * color bars or not. In previous revs we ifdef'd the test_gfx function out
- * but it's handy, especially when using a JTAG debugger
- * to be able to enable and disable a test graphics.
- */
-int show_test = 0;
-
-static void test_gfx(struct intel_dp *dp)
-{
- int i;
-
- if (!show_test)
- return;
- /* This is a sanity test code which fills the screen with two bands --
- green and blue. It is very useful to ensure all the initializations
- are made right. Thus, to be used only for testing, not otherwise
- */
-
- for (i = 0; i < (dp->edid.va - 4); i++) {
- u32 *l;
- int j;
- u32 tcolor = 0x0ff;
- for (j = 0; j < (dp->edid.ha-4); j++) {
- if (j == (dp->edid.ha/2)) {
- tcolor = 0xff00;
- }
- l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor));
- memcpy(l,&tcolor,sizeof(tcolor));
- }
- }
- printk(BIOS_SPEW, "sleep 10\n");
- delay(10);
-}
-
-void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
-{
- u32 ddi_pll_sel = 0;
-
- switch (intel_dp->link_bw) {
- case DP_LINK_BW_1_62:
- ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
- break;
- case DP_LINK_BW_2_7:
- ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
- break;
- case DP_LINK_BW_5_4:
- ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
- break;
- default:
- printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
- return;
- }
-
- gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
-}
-
-int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
-{
- int i;
- int edid_ok;
- int pixels = FRAME_BUFFER_BYTES/64;
-
- gtt_write(PCH_PP_CONTROL,0xabcd000f);
- delay(1);
-
- void runio(struct intel_dp *dp);
- /* hard codes -- stuff you can only know from the mainboard */
- dp->gen = 8; // This is gen 8 which we believe is Haswell
- dp->is_haswell = 1;
- dp->DP = 0x2;
- dp->pipe = PIPE_A;
- dp->port = PORT_A;
- dp->plane = PLANE_A;
- dp->pipe_bits_per_pixel = 24;
- dp->type = INTEL_OUTPUT_EDP;
- dp->output_reg = DP_A;
- /* observed from YABEL. */
- dp->aux_clock_divider = 0xe1;
- dp->precharge = 3;
-
- /* 1. Normal mode: Set the first page to zero and make
- all GTT entries point to the same page
- 2. Developer/Recovery mode: Set up a tasteful color
- so people know we are alive. */
- if (init_fb || show_test) {
- set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase,
- 4096);
- memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
- } else {
- set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
- memset((void*)dp->graphics, 0, 4096);
- }
-
- dp->address = 0x50;
-
- if ( !intel_dp_get_dpcd(dp) )
- goto fail;
-
- intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
- for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
- if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
- 0x50, &dp->rawedid[i]) < 0)
- break;
- dp->edidlen++;
- }
-
- edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
-
- printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
-
- compute_display_params(dp);
-
- printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
- dp->edid.pixel_clock, dp->edid.link_clock);
-
- intel_ddi_set_pipe_settings(dp);
-
- runio(dp);
-
- palette();
-
- pixels = dp->edid.ha * (dp->edid.va-4) * 4;
- printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
- test_gfx(dp);
-
- set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
- i915_init_done = 1;
- return 1;
-
-fail:
- printk(BIOS_SPEW, "Graphics could not be started;");
- /* unclear we will *ever* want to do this. */
- if (0){
- printk(BIOS_SPEW, "Turn off power and wait ...");
- gtt_write(PCH_PP_CONTROL,0xabcd0000);
- udelay(600000);
- gtt_write(PCH_PP_CONTROL,0xabcd000f);
- }
- printk(BIOS_SPEW, "Returning.\n");
- return 0;
-}
diff --git a/src/mainboard/google/auron/gpio.h b/src/mainboard/google/auron/gpio.h
index 147b914800..5452df81be 100644
--- a/src/mainboard/google/auron/gpio.h
+++ b/src/mainboard/google/auron/gpio.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,108 +17,108 @@
* Foundation, Inc.
*/
-#ifndef PEPPY_GPIO_H
-#define PEPPY_GPIO_H
+#ifndef AURON_GPIO_H
+#define AURON_GPIO_H
-struct pch_lp_gpio_map;
+#include <soc/gpio.h>
-const struct pch_lp_gpio_map mainboard_gpio_map[] = {
- LP_GPIO_UNUSED, /* 0: UNUSED */
- LP_GPIO_UNUSED, /* 1: UNUSED */
- LP_GPIO_UNUSED, /* 2: UNUSED */
- LP_GPIO_UNUSED, /* 3: UNUSED */
- LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
- LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
- LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
- LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
- LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
- LP_GPIO_INPUT, /* 9: RAM_ID1 */
- LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
- LP_GPIO_UNUSED, /* 11: UNUSED */
- LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
- LP_GPIO_INPUT, /* 13: RAM_ID0 */
- LP_GPIO_INPUT, /* 14: EC_IN_RW */
- LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
- LP_GPIO_UNUSED, /* 16: UNUSED */
- LP_GPIO_UNUSED, /* 17: UNUSED */
- LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
- LP_GPIO_UNUSED, /* 19: UNUSED */
- LP_GPIO_UNUSED, /* 20: UNUSED */
- LP_GPIO_UNUSED, /* 21: UNUSED */
- LP_GPIO_UNUSED, /* 22: UNUSED */
- LP_GPIO_UNUSED, /* 23: UNUSED */
- LP_GPIO_UNUSED, /* 24: UNUSED */
- LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
- LP_GPIO_UNUSED, /* 26: UNUSED */
- LP_GPIO_UNUSED, /* 27: UNUSED */
- LP_GPIO_UNUSED, /* 28: UNUSED */
- LP_GPIO_UNUSED, /* 29: UNUSED */
- LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
- LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
- LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
- LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
- LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
- LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
- LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
- LP_GPIO_UNUSED, /* 37: UNUSED */
- LP_GPIO_UNUSED, /* 38: UNUSED */
- LP_GPIO_UNUSED, /* 39: UNUSED */
- LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
- LP_GPIO_UNUSED, /* 41: UNUSED */
- LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
- LP_GPIO_UNUSED, /* 43: UNUSED */
- LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
- LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
- LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
- LP_GPIO_INPUT, /* 47: RAM_ID2 */
- LP_GPIO_UNUSED, /* 48: UNUSED */
- LP_GPIO_UNUSED, /* 49: UNUSED */
- LP_GPIO_UNUSED, /* 50: UNUSED */
- LP_GPIO_INPUT, /* 51: ALS_INT_L */
- LP_GPIO_INPUT, /* 52: SIM_DET */
- LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
- LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
- LP_GPIO_UNUSED, /* 55: UNUSED */
- LP_GPIO_UNUSED, /* 56: UNUSED */
- LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
- LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
- LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
- LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
- LP_GPIO_UNUSED, /* 61: UNUSED */
- LP_GPIO_UNUSED, /* 62: UNUSED */
- LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- LP_GPIO_UNUSED, /* 64: UNUSED */
- LP_GPIO_UNUSED, /* 65: UNUSED */
- LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
- LP_GPIO_UNUSED, /* 67: UNUSED */
- LP_GPIO_UNUSED, /* 68: UNUSED */
- LP_GPIO_UNUSED, /* 69: UNUSED */
- LP_GPIO_UNUSED, /* 70: UNUSED */
- LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
- LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
- LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
- LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
- LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
- LP_GPIO_UNUSED, /* 76: UNUSED */
- LP_GPIO_UNUSED, /* 77: UNUSED */
- LP_GPIO_UNUSED, /* 78: UNUSED */
- LP_GPIO_UNUSED, /* 79: UNUSED */
- LP_GPIO_UNUSED, /* 80: UNUSED */
- LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */
- LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
- LP_GPIO_UNUSED, /* 83: UNUSED */
- LP_GPIO_UNUSED, /* 84: UNUSED */
- LP_GPIO_UNUSED, /* 85: UNUSED */
- LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
- LP_GPIO_UNUSED, /* 87: UNUSED */
- LP_GPIO_UNUSED, /* 88: UNUSED */
- LP_GPIO_UNUSED, /* 89: UNUSED */
- LP_GPIO_UNUSED, /* 90: UNUSED */
- LP_GPIO_UNUSED, /* 91: UNUSED */
- LP_GPIO_UNUSED, /* 92: UNUSED */
- LP_GPIO_UNUSED, /* 93: UNUSED */
- LP_GPIO_UNUSED, /* 94: UNUSED */
- LP_GPIO_END
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
+ PCH_GPIO_INPUT, /* 9: RAM_ID1 */
+ PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
+ PCH_GPIO_UNUSED, /* 11: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
+ PCH_GPIO_INPUT, /* 13: RAM_ID0 */
+ PCH_GPIO_INPUT, /* 14: EC_IN_RW */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 16: UNUSED */
+ PCH_GPIO_UNUSED, /* 17: UNUSED */
+ PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_UNUSED, /* 20: UNUSED */
+ PCH_GPIO_UNUSED, /* 21: UNUSED */
+ PCH_GPIO_UNUSED, /* 22: UNUSED */
+ PCH_GPIO_UNUSED, /* 23: UNUSED */
+ PCH_GPIO_UNUSED, /* 24: UNUSED */
+ PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
+ PCH_GPIO_UNUSED, /* 26: UNUSED */
+ PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_UNUSED, /* 28: UNUSED */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
+ PCH_GPIO_UNUSED, /* 41: UNUSED */
+ PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
+ PCH_GPIO_UNUSED, /* 43: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
+ PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
+ PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
+ PCH_GPIO_INPUT, /* 47: RAM_ID2 */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_UNUSED, /* 49: UNUSED */
+ PCH_GPIO_UNUSED, /* 50: UNUSED */
+ PCH_GPIO_INPUT, /* 51: ALS_INT_L */
+ PCH_GPIO_INPUT, /* 52: SIM_DET */
+ PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
+ PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_UNUSED, /* 56: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
+ PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
+ PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
+ PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
+ PCH_GPIO_UNUSED, /* 61: UNUSED */
+ PCH_GPIO_UNUSED, /* 62: UNUSED */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
+ PCH_GPIO_UNUSED, /* 65: UNUSED */
+ PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 67: UNUSED */
+ PCH_GPIO_UNUSED, /* 68: UNUSED */
+ PCH_GPIO_UNUSED, /* 69: UNUSED */
+ PCH_GPIO_UNUSED, /* 70: UNUSED */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
+ PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
+ PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
+ PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_UNUSED, /* 83: UNUSED */
+ PCH_GPIO_UNUSED, /* 84: UNUSED */
+ PCH_GPIO_UNUSED, /* 85: UNUSED */
+ PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_UNUSED, /* 89: UNUSED */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_UNUSED, /* 91: UNUSED */
+ PCH_GPIO_UNUSED, /* 92: UNUSED */
+ PCH_GPIO_UNUSED, /* 93: UNUSED */
+ PCH_GPIO_UNUSED, /* 94: UNUSED */
+ PCH_GPIO_END
};
#endif
diff --git a/src/mainboard/google/auron/hda_verb.c b/src/mainboard/google/auron/hda_verb.h
index fc341b87d6..2fd30905b7 100644
--- a/src/mainboard/google/auron/hda_verb.c
+++ b/src/mainboard/google/auron/hda_verb.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -14,16 +14,19 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc.
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
+static const u32 mainboard_cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
0x10ec0283, // Subsystem ID
- 0x0000000c, // Number of jacks (NID entries)
+ 0x0000000d, // Number of jacks (NID entries)
+
+ 0x0017ff00, // Function Reset
+ 0x0017ff00, // Double Function Reset
+ 0x000F0000, // Pad - get vendor id
+ 0x000F0002, // Pad - get revision id
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
@@ -31,59 +34,72 @@ const u32 cim_verb_data[] = {
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
- AZALIA_SUBVENDOR(0x0, 0x10ec0283),
+ 0x00172083,
+ 0x00172102,
+ 0x001722ec,
+ 0x00172310,
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) DMIC - Disabled */
- AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
+ 0x01271cf0, //
+ 0x01271d11, //
+ 0x01271e11, //
+ 0x01271f41, //
/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
- // group 1, cap 0
- // no connector, no jack detect
- // speaker out, analog
- // fixed function, internal, Location N/A
- AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+ 0x01471c10, // group 1, cap 0
+ 0x01471d01, // no connector, no jack detect
+ 0x01471e17, // speaker out, analog
+ 0x01471f90, // fixed function, internal, Location N/A
/* Pin Complex (NID 0x17) MONO Out - Disabled */
- AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+ 0x01771cf0, //
+ 0x01771d11, //
+ 0x01771e11, //
+ 0x01771f41, //
/* Pin Complex (NID 0x18) Disabled */
- AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+ 0x01871cf0, //
+ 0x01871d11, //
+ 0x01871e11, //
+ 0x01871f41, //
/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
- // group2, cap 0
- // black, jack detect
- // Mic in, 3.5mm Jack
- // connector, External left panel
- AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
+ 0x01971c20, // group2, cap 0
+ 0x01971d10, // black, jack detect
+ 0x01971ea1, // Mic in, 3.5mm Jack
+ 0x01971f03, // connector, External left panel
/* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
- // group 1, cap 1
- // no connector, no jack detect
- // mic in, analog connection
- // Fixed function, internal, Location N/A
- AZALIA_PIN_CFG(0x0, 0x1a, 0x90a70111),
+ 0x01a71c11, // group 1, cap 1
+ 0x01a71d01, // no connector, no jack detect
+ 0x01a71ea7, // mic in, analog connection
+ 0x01a71f90, // Fixed function, internal, Location N/A
/* Pin Complex (NID 0x1B) LINE2 - Disabled */
- AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+ 0x01b71cf0, //
+ 0x01b71d11, //
+ 0x01b71e11, //
+ 0x01b71f41, //
/* Pin Complex (NID 0x1D) PCBeep */
- // eapd low on ex-amp, laptop, custom enable
- // mute spkr on hpout
- // pcbeep en able, checksum
- // no physical, Internal, Location N/A
- AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
+ 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
+ 0x01d71d81, // mute spkr on hpout
+ 0x01d71e15, // pcbeep en able, checksum
+ 0x01d71f40, // no physical, Internal, Location N/A
/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
- AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+ 0x01e71cf0, //
+ 0x01e71d11, //
+ 0x01e71e11, //
+ 0x01e71f41, //
/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
- // group2, cap 1
- // black, jack detect
- // HPOut, 3.5mm Jack
- // connector, left panel
- AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
+ 0x02171c21, // group2, cap 1
+ 0x02171d10, // black, jack detect
+ 0x02171e21, // HPOut, 3.5mm Jack
+ 0x02171f03, // connector, left panel
/* Undocumented settings from Realtek (needed for beep_gen) */
/* Widget node 0x20 */
@@ -93,7 +109,7 @@ const u32 cim_verb_data[] = {
0x0204081b,
};
-const u32 pc_beep_verbs[] = {
+static const u32 mainboard_pc_beep_verbs[] = {
0x00170500, /* power up everything (codec, dac, adc, mixers) */
0x01470740, /* enable speaker out */
0x01470c02, /* set speaker EAPD pin */
@@ -102,4 +118,5 @@ const u32 pc_beep_verbs[] = {
0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
};
-AZALIA_ARRAY_SIZES;
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/google/auron/i915io.c b/src/mainboard/google/auron/i915io.c
deleted file mode 100644
index eb7b136be2..0000000000
--- a/src/mainboard/google/auron/i915io.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc.
-*/
-
-#include <stdint.h>
-#include <console/console.h>
-#include <delay.h>
-#include <drivers/intel/gma/i915.h>
-#include <arch/io.h>
-#include "mainboard.h"
-
-void runio(struct intel_dp *dp, int verbose);
-void runio(struct intel_dp *dp, int verbose)
-{
- u8 read_val;
- gtt_write(DDI_BUF_CTL_A,
- DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
- |0x00000091);
-
- intel_prepare_ddi();
-
- gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
- gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
- gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
-
- gtt_write(DEIIR,0x00008000);
- intel_dp_wait_reg(DEIIR, 0x00000000);
- gtt_write(DSPSTRIDE(dp->plane), dp->stride);
- gtt_write(DSPADDR(dp->plane), 0x00000000);
-
- printk(BIOS_SPEW, "DP_SET_POWER");
-
- intel_dp_sink_dpms(dp, 0);
-
- intel_dp_set_m_n_regs(dp);
-
- intel_dp_get_max_downspread(dp, &read_val);
-
- intel_dp_set_resolution(dp);
-
- gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
- gtt_write(PIPECONF(dp->transcoder),0x00000000);
- gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
-
- mainboard_set_port_clk_dp(dp);
-
- gtt_write(DSPSTRIDE(dp->plane),dp->stride);
- gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
-
- gtt_write(DEIIR,0x00000080);
- intel_dp_wait_reg(DEIIR, 0x00000000);
-
- /* There is some reason we removed these three calls from
- * slippy/gma.c -- I dont remember why!! */
- gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
- gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
- gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
-
- gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
- gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
-
- /* what is this doing? Not sure yet. But we don't seem to be
- * able to live without it.*/
- intel_dp_i2c_write(dp, 0x0);
- intel_dp_i2c_read(dp, &read_val);
- intel_dp_i2c_write(dp, 0x04);
- intel_dp_i2c_read(dp, &read_val);
- intel_dp_i2c_write(dp, 0x7e);
- intel_dp_i2c_read(dp, &read_val);
-
- gtt_write(DDI_BUF_CTL_A,
- DDI_BUF_IS_IDLE|
- DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
- |0x00000091);
-
- gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
- gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
- DP_TP_CTL_ENHANCED_FRAME_ENABLE);
-
- gtt_write(DDI_BUF_CTL_A,
- DDI_BUF_CTL_ENABLE|
- /* another undocumented setting. Surprised? */ 0x40000 |
- DDI_BUF_IS_IDLE|DDI_A_4_LANES|
- DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
- 0x80040091);
-
- intel_dp_set_bw(dp);
-
- intel_dp_set_lane_count(dp);
-
- mainboard_train_link(dp);
-
- gtt_write(DP_TP_CTL(dp->port),
- DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
- DP_TP_CTL_LINK_TRAIN_IDLE);
-
- gtt_write(DP_TP_CTL(dp->port),
- DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
- DP_TP_CTL_LINK_TRAIN_NORMAL);
-
- gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
- gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
- gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
-
- /* some of this is not needed. But with a total lack of docs, well ...*/
- gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
-
- gtt_write(SDEIIR,0x00000000);
- gtt_write(DEIIR,0x00000000);
- gtt_write(DEIIR,0x00008000);
- intel_dp_wait_reg(DEIIR, 0x00000000);
-
- gtt_write(DSPSTRIDE(dp->plane),dp->stride);
- gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
-
- gtt_write(DEIIR,0x00000080);
- intel_dp_wait_reg(DEIIR, 0x00000000);
-
- gtt_write(DSPSTRIDE(dp->plane),dp->stride);
- gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-
- gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
-
- gtt_write(SDEIIR,0x00000000);
- gtt_write(SDEIIR,0x00000000);
- gtt_write(DEIIR,0x00000000);
-
-}
diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c
index 1a2216cd5a..cc9907eb0c 100644
--- a/src/mainboard/google/auron/mainboard.c
+++ b/src/mainboard/google/auron/mainboard.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,17 +32,26 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
-#include <southbridge/intel/lynxpoint/pch.h>
+#include "hda_verb.h"
#include "ec.h"
#include "onboard.h"
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
+/* Audio Setup */
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 *pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
static void mainboard_init(device_t dev)
{
@@ -74,6 +83,15 @@ static int mainboard_smbios_data(device_t dev, int *handle,
len += smbios_write_type41(
current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_GEN5_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ len += smbios_write_type41(
+ current, handle,
BOARD_TOUCHSCREEN_NAME, /* name */
BOARD_TOUCHSCREEN_IRQ, /* instance */
BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
@@ -92,6 +110,7 @@ static void mainboard_enable(device_t dev)
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+ verb_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/auron/mainboard.h b/src/mainboard/google/auron/mainboard.h
deleted file mode 100644
index f1decee193..0000000000
--- a/src/mainboard/google/auron/mainboard.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc.
-*/
-
-#ifndef __MAINBOARD_H_
-#define __MAINBOARD_H_
-void mainboard_train_link(struct intel_dp *intel_dp);
-void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
-
-#endif
diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h
index 0f717a1eae..c9b8696179 100644
--- a/src/mainboard/google/auron/onboard.h
+++ b/src/mainboard/google/auron/onboard.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -30,6 +30,7 @@
#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
#define BOARD_TRACKPAD_I2C_ADDR 0x67
+#define BOARD_TRACKPAD_GEN5_I2C_ADDR 0x24
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */
@@ -37,7 +38,4 @@
#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
-#define PEPPY_BOARD_VERSION_PROTO 0
-#define PEPPY_BOARD_VERSION_EVT 1
-
#endif
diff --git a/src/mainboard/google/auron/pei_data.c b/src/mainboard/google/auron/pei_data.c
new file mode 100644
index 0000000000..779a62b6d6
--- /dev/null
+++ b/src/mainboard/google/auron/pei_data.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel -- can be changed by SPD init */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ /* P0: LTE */
+ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P1: POrt A, CN10 */
+ pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P2: CCD */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P3: BT */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_MINI_PCIE);
+ /* P4: Port B, CN6 */
+ pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+ USB_PORT_BACK_PANEL);
+ /* P5: EMPTY */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: SD Card */
+ pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FLEX);
+ /* P7: EMPTY */
+ pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+
+ /* P1: Port A, CN6 */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: EMPTY */
+ pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
+ /* P3: EMPTY */
+ pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+ /* P4: EMPTY */
+ pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c
index 695778346e..17279e3e72 100644
--- a/src/mainboard/google/auron/romstage.c
+++ b/src/mainboard/google/auron/romstage.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,170 +18,35 @@
* Foundation, Inc.
*/
-#include <delay.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
#include <cbfs.h>
#include <console/console.h>
-#include <cpu/intel/haswell/haswell.h>
-#include "ec/google/chromeec/ec.h"
-#include <northbridge/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/raminit.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include <mainboard/google/auron/spd/spd.h>
#include "gpio.h"
-#include "onboard.h"
-
-const struct rcba_config_instruction rcba_config[] = {
-
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP PCIE INTA -> PIRQA
- * D29IP_E1P EHCI INTA -> PIRQD
- * D20IP_XHCI XHCI INTA -> PIRQC (MSI)
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
- RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
- RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP)),
- RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
- RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
- RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
- RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
-
- /* Device interrupt route registers */
- RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
- RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
- RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
- RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
- RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
- RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
- RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
- RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
-
- /* Disable unused devices (board specific) */
- RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
- RCBA_END_CONFIG,
-};
-
-/* Copy SPD data for on-board memory */
-static void copy_spd(struct pei_data *peid)
+void mainboard_romstage_entry(struct romstage_params *rp)
{
- const int gpio_vector[] = {13, 9, 47, -1};
- int spd_index = get_gpios(gpio_vector);
- char *spd_file;
- size_t spd_file_len;
-
- printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- switch (google_chromeec_get_board_version()) {
- case PEPPY_BOARD_VERSION_PROTO:
- /* Index 0 is 2GB config with CH0 only. */
- if (spd_index == 0)
- peid->dimm_channel1_disabled = 3;
- break;
-
- case PEPPY_BOARD_VERSION_EVT:
- default:
- /* Index 0-2 are 4GB config with both CH0 and CH1.
- * Index 4-6 are 2GB config with CH0 only. */
- if (spd_index > 3)
- peid->dimm_channel1_disabled = 3;
- break;
- }
+ struct pei_data pei_data;
- if (spd_file_len <
- ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
+ post_code(0x32);
- if (spd_file_len < sizeof(peid->spd_data[0]))
- die("Missing SPD data.");
+ /* Ensure the EC is in the right mode for recovery */
+ google_chromeec_early_init();
- memcpy(peid->spd_data[0],
- spd_file +
- spd_index * sizeof(peid->spd_data[0]),
- sizeof(peid->spd_data[0]));
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
- struct pei_data pei_data = {
- .pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = DEFAULT_PCIEXBAR,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
- .ec_present = 1,
- // 0 = leave channel enabled
- // 1 = disable dimm 0 on channel
- // 2 = disable dimm 1 on channel
- // 3 = disable dimm 0+1 on channel
- .dimm_channel0_disabled = 2,
- .dimm_channel1_disabled = 2,
- .max_ddr3_freq = 1600,
- .usb_xhci_on_resume = 1,
- .usb2_ports = {
- /* Length, Enable, OCn#, Location */
- { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 0, /* P1: Port A, CN10 */
- USB_PORT_BACK_PANEL },
- { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 2, /* P4: Port B, CN6 */
- USB_PORT_BACK_PANEL },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
- USB_PORT_SKIP },
- { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
- USB_PORT_FLEX },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
- USB_PORT_SKIP },
- },
- .usb3_ports = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; Port A, CN6 */
- { 0, USB_OC_PIN_SKIP }, /* P2; */
- { 0, USB_OC_PIN_SKIP }, /* P3; */
- { 0, USB_OC_PIN_SKIP }, /* P4; */
- },
- };
+ /* Initialize GPIOs */
+ init_gpios(mainboard_gpio_config);
- struct romstage_params romstage_params = {
- .pei_data = &pei_data,
- .gpio_map = &mainboard_gpio_map,
- .rcba_config = &rcba_config[0],
- .bist = bist,
- .copy_spd = copy_spd,
- };
+ /* Fill out PEI DATA */
+ memset(&pei_data, 0, sizeof(pei_data));
+ mainboard_fill_pei_data(&pei_data);
+ mainboard_fill_spd_data(&pei_data);
+ rp->pei_data = &pei_data;
/* Call into the real romstage main with this board's attributes. */
- romstage_common(&romstage_params);
+ romstage_common(rp);
}
diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index 5d7df375ae..2f46260f0b 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
- * Copyright 2012 Google Inc.
+ * Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,15 +21,15 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
#include <elog.h>
-
-/* Include EC functions */
#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
#include "ec.h"
/* Codec enable: GPIO45 */
@@ -37,6 +37,7 @@
/* WLAN / BT enable: GPIO46 */
#define GPIO_WLAN_DISABLE_L 46
+
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
@@ -53,9 +54,9 @@ static u8 mainboard_smi_ec(void)
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
- pm1_cnt = inl(get_pmbase() + PM1_CNT);
+ pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, get_pmbase() + PM1_CNT);
+ outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
break;
}
@@ -67,7 +68,8 @@ void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
/* Process all pending events */
- while (mainboard_smi_ec() != 0);
+ while (mainboard_smi_ec() != 0)
+ ;
}
}
@@ -76,12 +78,12 @@ void mainboard_smi_sleep(u8 slp_typ)
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
- if (smm_get_gnvs()->s3u0 == 0)
+ if (smm_get_gnvs()->s3u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
- if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
+ }
set_gpio(GPIO_PP3300_CODEC_EN, 0);
set_gpio(GPIO_WLAN_DISABLE_L, 0);
@@ -90,12 +92,12 @@ void mainboard_smi_sleep(u8 slp_typ)
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case 5:
- if (smm_get_gnvs()->s5u0 == 0)
+ if (smm_get_gnvs()->s5u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
- if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
+ }
set_gpio(GPIO_PP3300_CODEC_EN, 0);
set_gpio(GPIO_WLAN_DISABLE_L, 0);
@@ -110,37 +112,25 @@ void mainboard_smi_sleep(u8 slp_typ)
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
- while (google_chromeec_get_event() != 0);
+ while (google_chromeec_get_event() != 0)
+ ;
}
-
-static int mainboard_finalized = 0;
-
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
- case APM_CNT_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_pch_finalize_smm();
- intel_northbridge_haswell_finalize_smm();
- intel_cpu_haswell_finalize_smm();
-
- mainboard_finalized = 1;
- break;
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
- while (google_chromeec_get_event() != 0);
+ while (google_chromeec_get_event() != 0)
+ ;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
- while (google_chromeec_get_event() != 0);
+ while (google_chromeec_get_event() != 0)
+ ;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
diff --git a/src/mainboard/google/auron/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex
index eb41f0bfb1..eb41f0bfb1 100644
--- a/src/mainboard/google/auron/Elpida_EDJ4216EFBG.spd.hex
+++ b/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex
diff --git a/src/mainboard/google/auron/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex
index 7b0932743d..7b0932743d 100644
--- a/src/mainboard/google/auron/Hynix_HMT425S6AFR6A.spd.hex
+++ b/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex
diff --git a/src/mainboard/google/auron/spd/Makefile.inc b/src/mainboard/google/auron/spd/Makefile.inc
new file mode 100644
index 0000000000..7b0292d826
--- /dev/null
+++ b/src/mainboard/google/auron/spd/Makefile.inc
@@ -0,0 +1,54 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO47, GPIO9, GPIO13 }
+SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
+SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0010
+SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
+SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
+SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0110
+SPD_SOURCES += empty # 0b0111
+SPD_SOURCES += empty # 0b1000
+SPD_SOURCES += empty # 0b1001
+SPD_SOURCES += empty # 0b1010
+SPD_SOURCES += empty # 0b1011
+SPD_SOURCES += empty # 0b1100
+SPD_SOURCES += empty # 0b1101
+SPD_SOURCES += empty # 0b1110
+SPD_SOURCES += empty # 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do echo -e -n "\\x$$c"; \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab
diff --git a/src/mainboard/google/auron/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex
index cbe9e4fbfe..cbe9e4fbfe 100644
--- a/src/mainboard/google/auron/Micron_4KTF25664HZ.spd.hex
+++ b/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex
diff --git a/src/mainboard/google/auron/spd/empty.spd.hex b/src/mainboard/google/auron/spd/empty.spd.hex
new file mode 100644
index 0000000000..9ec39f1ba4
--- /dev/null
+++ b/src/mainboard/google/auron/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/spd/spd.c b/src/mainboard/google/auron/spd/spd.c
new file mode 100644
index 0000000000..2f3f20c2e2
--- /dev/null
+++ b/src/mainboard/google/auron/spd/spd.c
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <mainboard/google/auron/gpio.h>
+#include <mainboard/google/auron/spd/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+ , banks, ranks, rows, cols);
+ printk(BIOS_INFO, "density %d Mb\n", capmb);
+
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int spd_bits[3] = {
+ SPD_GPIO_BIT0,
+ SPD_GPIO_BIT1,
+ SPD_GPIO_BIT2
+ };
+ int spd_gpio[3];
+ int spd_index;
+ size_t spd_file_len;
+ char *spd_file;
+
+ spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+ spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+ spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+
+ spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
+
+ printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+ spd_index,
+ spd_bits[2], spd_gpio[2],
+ spd_bits[1], spd_gpio[1],
+ spd_bits[0], spd_gpio[0]);
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (spd_index > 3)
+ pei_data->dimm_channel1_disabled = 3;
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ memcpy(pei_data->spd_data[0][0],
+ spd_file + spd_index, SPD_LEN);
+ /* Index 0-2 are 4GB config with both CH0 and CH1.
+ * Index 4-6 are 2GB config with CH0 only. */
+ if (spd_index > 3)
+ pei_data->dimm_channel1_disabled = 3;
+ else
+ memcpy(pei_data->spd_data[1][0],
+ spd_file + spd_index, SPD_LEN);
+
+ /* Make sure a valid SPD was found */
+ if (pei_data->spd_data[0][0][0] == 0)
+ die("Invalid SPD data.");
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/spd/spd.h b/src/mainboard/google/auron/spd/spd.h
new file mode 100644
index 0000000000..27b1a4e226
--- /dev/null
+++ b/src/mainboard/google/auron/spd/spd.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+/* Auron board memory configuration GPIOs */
+#define SPD_GPIO_BIT0 13
+#define SPD_GPIO_BIT1 9
+#define SPD_GPIO_BIT2 47
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/thermal.h b/src/mainboard/google/auron/thermal.h
index e9f46887e6..48579f1376 100644
--- a/src/mainboard/google/auron/thermal.h
+++ b/src/mainboard/google/auron/thermal.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -23,16 +23,17 @@
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 0 /* PECI */
#define CTL_TDP_POWER_LIMIT 12 /* 12W */
-#define CTL_TDP_THRESHOLD_OFF 80 /* Normal at 80C */
-#define CTL_TDP_THRESHOLD_ON 85 /* Limited at 85C */
+#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
+#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
+#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 99
+#define CRITICAL_TEMPERATURE 104
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 95
/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 100
+#define MAX_TEMPERATURE 105
#endif