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| author | Martin Roth <martinroth@chromium.org> | 2020-02-05 16:46:30 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:49:08 +0000 |
| commit | dafcc7a26dece2cbd73a6a4f761b3fb3963bd260 (patch) | |
| tree | 49c86ce6988e785adff903d8b8814294a98e9806 | |
| parent | a616a4be366c6af1f8ccfbfd1f16a4572c7e6c91 (diff) | |
| download | coreboot-dafcc7a26dece2cbd73a6a4f761b3fb3963bd260.tar.xz | |
Rework map_oprom_vendev to add revision check and mapping
AMD's Family 17h SoCs share the same video device ID, but may need
different video BIOSes. This adds the common code changes to check the
vendor & device IDs along with the revision and select the correct video
BIOS to use.
Change-Id: I2978a5693c904ddb09d23715cb309c4a356e0370
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/2040455
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/device/pci_rom.c | 27 | ||||
| -rw-r--r-- | src/include/device/pci_rom.h | 1 |
2 files changed, 17 insertions, 11 deletions
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 6af20e854e..7d489615f1 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -23,29 +23,34 @@ #include <arch/acpigen.h> /* Rmodules don't like weak symbols. */ +void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; } u32 __weak map_oprom_vendev(u32 vendev) { return vendev; } struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header = NULL; struct pci_data *rom_data; + u8 rev = pci_read_config8(dev, PCI_REVISION_ID); + u8 mapped_rev = rev; + u32 vendev = (dev->vendor << 16) | dev->device; + u32 mapped_vendev = vendev; - /* If it's in FLASH, then don't check device for ROM. */ + /* If the ROM is in flash, then don't check the PCI device for it. */ if (CONFIG(CHECK_REV_IN_OPROM_NAME)) { - uint8_t rev = pci_read_config8(dev, PCI_REVISION_ID); rom_header = cbfs_boot_map_optionrom_revision(dev->vendor, dev->device, rev); - } - - if (!rom_header) + map_oprom_vendev_rev(&mapped_vendev, &mapped_rev); + } else { rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); - - u32 vendev = (dev->vendor << 16) | dev->device; - u32 mapped_vendev; - - mapped_vendev = map_oprom_vendev(vendev); + mapped_vendev = map_oprom_vendev(vendev); + } if (!rom_header) { - if (vendev != mapped_vendev) { + if (CONFIG(CHECK_REV_IN_OPROM_NAME) && + (vendev != mapped_vendev || rev != mapped_rev)) { + rom_header = cbfs_boot_map_optionrom_revision( + mapped_vendev >> 16, + mapped_vendev & 0xffff, mapped_rev); + } else if (vendev != mapped_vendev) { rom_header = cbfs_boot_map_optionrom( mapped_vendev >> 16, mapped_vendev & 0xffff); diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 82f3c40005..47db52cf19 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -45,6 +45,7 @@ pci_rom_write_acpi_tables(struct device *device, void pci_rom_ssdt(struct device *device); +void map_oprom_vendev_rev(u32 *vendev, u8 *rev); u32 map_oprom_vendev(u32 vendev); int verified_boot_should_run_oprom(struct rom_header *rom_header); |