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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-06 10:40:07 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-08-20 06:58:02 +0000 |
| commit | ddcf5a05e3168fbb4565a2a52c14c246822454b2 (patch) | |
| tree | ff1c7c1497641fbeb3e9161f901231579fb5f0e9 | |
| parent | e051dc07f56159936c7410118dc364a108812f8c (diff) | |
| download | coreboot-ddcf5a05e3168fbb4565a2a52c14c246822454b2.tar.xz | |
mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functions
Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/asus/kfsn4-dre/romstage.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 2809f0fe91..cc198c6975 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,9 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize GPIO */ /* Access SuperIO GPI03 logical device */ - uint16_t port = GPIO3_DEV >> 8; - outb(0x87, port); - outb(0x87, port); + pnp_enter_conf_state(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV); /* Set GP37 (power LED) to output */ pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); @@ -355,7 +353,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); /* Restore default SuperIO access */ - outb(0xaa, port); + pnp_exit_conf_state(GPIO3_DEV); } /** |