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| author | Christian Walter <christian.walter@9elements.com> | 2020-04-27 18:11:51 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2020-05-04 14:20:17 +0000 |
| commit | e01054d86eecfff846764e640eaafe58b5d5fb5d (patch) | |
| tree | 443a196cd883e6b8e89b947f612fdcabda56fd94 | |
| parent | 066007590f5b904962f9965ace5485ddab7a89c3 (diff) | |
| download | coreboot-e01054d86eecfff846764e640eaafe58b5d5fb5d.tar.xz | |
soc/intel/cannonlake: Add DisableHeciRetry to config
Add DisableHeciRetry to the chip config and parse it in romstage.
Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b74291ebb3..d4d76cdb61 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -194,6 +194,7 @@ struct soc_intel_cannonlake_config { /* Heci related */ uint8_t Heci3Enabled; + uint8_t DisableHeciRetry; /* Gfx related */ uint8_t IgdDvmt50PreAlloc; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 010d152c76..7af90a73ed 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -128,6 +128,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) config->sata_port[i].TxGen3DeEmph; } } +#if !CONFIG(SOC_INTEL_COMETLAKE) + if (config->DisableHeciRetry) + tconfig->DisableHeciRetry = config->DisableHeciRetry; +#endif } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |