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authorDuncan Laurie <dlaurie@google.com>2017-08-10 16:27:48 -0700
committerMartin Roth <martinroth@google.com>2017-08-17 11:28:24 +0000
commite0b5795b81352aabe72662f48d6b154800021d34 (patch)
tree21c2eec140904fcec3d521e3c597e6d8ea701353
parent992d8a7711808e7c9ce61c4714d4040ca1cd7e28 (diff)
downloadcoreboot-e0b5795b81352aabe72662f48d6b154800021d34.tar.xz
soc/intel/skylake: Configure FSP to skip ME MBP step
We do not need or use the Management Engine MBP HOB so that step can be skipped when FSP initializes the ME. BUG=b:64479422 TEST=boot with FSP debug enabled binary and ensure that the output indicates this step is being skipped: Skipping MBP data due to SkipMbpHob set! Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/20951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index e439d73479..c43bdc300c 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -222,6 +222,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
soc_memory_init_params(m_cfg, config);
+ /* Skip creating Management Engine MBP HOB */
+ m_t_cfg->SkipMbpHob = 0x01;
+
/* Enable DMI Virtual Channel for ME */
m_t_cfg->DmiVcm = 0x01;