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authorIru Cai <mytbk920423@gmail.com>2019-06-13 10:57:21 +0800
committerIru Cai <mytbk920423@gmail.com>2019-11-17 15:10:46 +0800
commite0c632d073768f1b553b7cd0888194481107ab25 (patch)
treeaeab62dfde9c84d170ec78bfb52d465332bd6d84
parente8b75d1b9aa45c8c262576b1d80fc7014ebc60e6 (diff)
downloadcoreboot-e0c632d073768f1b553b7cd0888194481107ab25.tar.xz
mrc_frags.c: pci_devfn_t
-rw-r--r--src/northbridge/intel/haswell/mrc_frags.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/mrc_frags.c b/src/northbridge/intel/haswell/mrc_frags.c
index d20058b595..875ca2d9a8 100644
--- a/src/northbridge/intel/haswell/mrc_frags.c
+++ b/src/northbridge/intel/haswell/mrc_frags.c
@@ -436,7 +436,7 @@ void frag_usb_fffaed46(PEI_USB *upd, void *xbar)
int sku = mrc_sku_type();
int rev = mrc_pch_revision();
u32 tmp1, tmp2;
- device_t dev = PCI_DEV(0, 0x14, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 0);
/* XBAR is e8100000
printk(BIOS_DEBUG, "XBAR is %p.\n", xbar);
@@ -529,7 +529,7 @@ void frag_usb_fffaeb10(PEI_USB *upd, void *ebar)
return;
for (int i = 0; i < nb_ehci_dev; i++) {
- device_t dev = PCI_DEV(0, ehci_dev[i], 0);
+ pci_devfn_t dev = PCI_DEV(0, ehci_dev[i], 0);
if ((upd->xhci_resume_info[i] & 1) == 0) {
pci_write_config32(dev, 0x10, 0); // MEM_BASE
@@ -595,7 +595,7 @@ void frag_usb_fffaeb10(PEI_USB *upd, void *ebar)
void set_usb_overcurrent(PEI_USB *upd);
void set_usb_overcurrent(PEI_USB *upd)
{
- device_t dev = PCI_DEV(0, 0x14, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 0);
u32 u2ocm1 = 0;
u32 u2ocm2 = 0;