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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-12 11:48:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 12:11:08 +0000 |
| commit | e124fa5a9d48d7248a1a1987805b9c1ac2bdbde8 (patch) | |
| tree | 340f2de700107b6cbd0d34bf2e0814d5c65afd50 | |
| parent | ec3c8b552dc5334208e7579076afe1a45753363d (diff) | |
| download | coreboot-e124fa5a9d48d7248a1a1987805b9c1ac2bdbde8.tar.xz | |
drivers/intel/fsp1_1: Print the MTRR's FSP-T set up
Change-Id: I19e9038eb52922fa0c248936438f27789d00ddb5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
| -rw-r--r-- | src/drivers/intel/fsp1_1/car.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 79dd3681c3..3a41e40468 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -64,6 +64,8 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); + display_mtrrs(); + if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || car_params->bootloader_car_end != (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { |