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authorFurquan Shaikh <furquan@google.com>2020-06-18 23:14:51 -0700
committerFurquan Shaikh <furquan@google.com>2020-07-01 17:54:22 +0000
commite266eb82d9fc84b3c1c1e09c677e8b5d839626bb (patch)
tree39178b14e7a82de35f3455e78c4e1c2460a71d5c
parent94dfaad7253a1982b7feaf1bf7b1e4f1c872595d (diff)
downloadcoreboot-e266eb82d9fc84b3c1c1e09c677e8b5d839626bb.tar.xz
mb/google/zork: Add support for GPIO configuration on sleep path
This change adds support to configure GPIOs on the sleep path. This is required to turn off power to devices that do not act as wake sources and to assert reset to devices. Currently, variant_sleep_gpio_table() returns an empty table by default. In the following changes, entries will be added to gpio_sleep_table. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253642 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/mainboard/google/zork/smihandler.c9
-rw-r--r--src/mainboard/google/zork/variants/baseboard/Makefile.inc2
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c9
-rw-r--r--src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h7
4 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c
index 7c88215ecb..12a3b64c20 100644
--- a/src/mainboard/google/zork/smihandler.c
+++ b/src/mainboard/google/zork/smihandler.c
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+
#include <acpi/acpi.h>
+#include <baseboard/variants.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/smm.h>
#include <gpio.h>
@@ -15,10 +17,17 @@ void mainboard_smi_gpi(u32 gpi_sts)
}
void mainboard_smi_sleep(u8 slp_typ)
{
+ size_t num_gpios;
+ const struct soc_amd_gpio *gpios;
+
if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
+
+ gpios = variant_sleep_gpio_table(&num_gpios, slp_typ);
+ program_gpios(gpios, num_gpios);
}
+
int mainboard_smi_apmc(u8 apmc)
{
if (CONFIG(EC_GOOGLE_CHROMEEC))
diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc
index 7e4ccae4f3..0f025e0d84 100644
--- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc
@@ -24,6 +24,8 @@ ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += fsps_baseboard_dalboz.c
ramstage-y += helpers.c
ramstage-y += tpm_tis.c
+smm-y += gpio_baseboard_common.c
+
# Add OEM ID table
ifeq ($(CONFIG_USE_OEM_BIN),y)
cbfs-files-y += oem.bin
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index a4e86487bd..614e837726 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -30,3 +30,12 @@ const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
*size = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
+
+static const struct soc_amd_gpio gpio_sleep_table[] = {
+};
+
+const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ)
+{
+ *size = ARRAY_SIZE(gpio_sleep_table);
+ return gpio_sleep_table;
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
index 4f8f225ad1..6c5b95b5cc 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
@@ -25,6 +25,13 @@ const struct soc_amd_gpio *variant_base_gpio_table(size_t *size);
* configuration provided by variant_base_gpio_table().
*/
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
+
+/*
+ * This function provides GPIO table for the pads that need to be configured when entering
+ * sleep.
+ */
+const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ);
+
void variant_romstage_entry(void);
/* Modify devictree settings during ramstage. */
void variant_devtree_update(void);