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authorAamir Bohra <aamir.bohra@intel.com>2019-01-10 19:31:34 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-01-14 11:58:05 +0000
commite49b2f088f64b4a746491791c8e3727781a4ebb3 (patch)
treedda9d6b206e1a1e3d87c888dafd69c2947b2f934
parent522a1b526b31c66aed2d75e99dd810dc5a136bbf (diff)
downloadcoreboot-e49b2f088f64b4a746491791c8e3727781a4ebb3.tar.xz
mb/google/hatch: Use USB2 Port 10 for BT over CnVi
Integrated BT controller in CnVi uses USB port 10 for communication. BUG=b:122552619 TEST=lsusb shows BT device Change-Id: Iad1ca0e9419b534f50a3ce3fdcbd660caf8efb5c Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30809 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index ca045076bd..8dd2d849be 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -58,7 +58,7 @@ chip soc/intel/cannonlake
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
- register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1