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authorFrans Hendriks <fhendriks@eltan.com>2019-05-01 10:48:31 +0200
committerMatt DeVillier <matt.devillier@gmail.com>2019-05-03 22:39:14 +0000
commite6bf51fb221db651c271115b32f1308983d20987 (patch)
treed5f5cb3ea260cc868f38e166707e7dd5cbfd791a
parenta88041c04315cd2875cdf71e8070a6c7faa355a3 (diff)
downloadcoreboot-e6bf51fb221db651c271115b32f1308983d20987.tar.xz
{soc, southbridge} : Correct typo in comment
BUG=N/A TEST=N/A Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/braswell/southcluster.c2
-rw-r--r--src/southbridge/intel/bd82x6x/pch.c2
-rw-r--r--src/southbridge/intel/lynxpoint/pch.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 000790d9a6..bf9f689c2a 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -347,7 +347,7 @@ static void sc_init(struct device *dev)
* Common code for the south cluster devices.
*/
-/* Set bit in function disble register to hide this device. */
+/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(struct device *dev)
{
void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 746c11a2e3..f8540af451 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -144,7 +144,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
}
#ifndef __SMM__
-/* Set bit in Function Disble register to hide this device */
+/* Set bit in function disable register to hide this device */
static void pch_hide_devfn(unsigned devfn)
{
switch (devfn) {
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 5cf67aa238..a57bae311d 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -100,7 +100,7 @@ static void pch_enable_d3hot(struct device *dev)
pci_write_config32(dev, PCH_PCS, reg32);
}
-/* Set bit in Function Disble register to hide this device */
+/* Set bit in function disable register to hide this device */
void pch_disable_devfn(struct device *dev)
{
switch (dev->path.pci.devfn) {