soc/amd/stoneyridge: unify and align include guards with picasso

Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47582
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 33 insertions, 33 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
index 9617b45eca..19f0c81136 100644
--- a/src/soc/amd/stoneyridge/include/soc/acpi.h
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef __SOC_STONEYRIDGE_ACPI_H__
-#define __SOC_STONEYRIDGE_ACPI_H__
+#ifndef AMD_STONEYRIDGE_ACPI_H
+#define AMD_STONEYRIDGE_ACPI_H
 
 #include <acpi/acpi.h>
 
@@ -16,4 +16,4 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
 
 const char *soc_acpi_name(const struct device *dev);
 
-#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
+#endif /* AMD_STONEYRIDGE_ACPI_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
index c32786322c..3b54076ddd 100644
--- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __AMD_PCI_INT_DEFS_H__
-#define __AMD_PCI_INT_DEFS_H__
+#ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
+#define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
 
 /*
  * PIRQ and device routing - these define the index into the
@@ -44,4 +44,4 @@
 #define PIRQ_UART0	0x74
 #define PIRQ_UART1	0x75
 
-#endif /* __AMD_PCI_INT_DEFS_H__ */
+#endif /* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h
index 8d25fb6d4e..528daa4125 100644
--- a/src/soc/amd/stoneyridge/include/soc/cpu.h
+++ b/src/soc/amd/stoneyridge/include/soc/cpu.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __STONEYRIDGE_CPU_H__
-#define __STONEYRIDGE_CPU_H__
+#ifndef AMD_STONEYRIDGE_CPU_H
+#define AMD_STONEYRIDGE_CPU_H
 
 /*
  *  Set a variable MTRR in bootblock and/or romstage.  AGESA will use the lowest
@@ -16,4 +16,4 @@
 
 void check_mca(void);
 
-#endif /* __STONEYRIDGE_CPU_H__ */
+#endif /* AMD_STONEYRIDGE_CPU_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 02cc1884a5..8bfb1f606b 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __STONEYRIDGE_GPIO_H__
-#define __STONEYRIDGE_GPIO_H__
+#ifndef AMD_STONEYRIDGE_GPIO_H
+#define AMD_STONEYRIDGE_GPIO_H
 
 #define GPIO_DEVICE_NAME	"AMD0030"
 #define GPIO_DEVICE_DESC	"GPIO Controller"
@@ -292,4 +292,4 @@
 #define GPIO_2_EVENT GEVENT_8
 
 #endif /* __ACPI__ */
-#endif /* __STONEYRIDGE_GPIO_H__ */
+#endif /* AMD_STONEYRIDGE_GPIO_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h
index 63db7d4b16..0b61329fef 100644
--- a/src/soc/amd/stoneyridge/include/soc/i2c.h
+++ b/src/soc/amd/stoneyridge/include/soc/i2c.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __STONEYRIDGE_I2C_H__
-#define __STONEYRIDGE_I2C_H__
+#ifndef AMD_STONEYRIDGE_I2C_H
+#define AMD_STONEYRIDGE_I2C_H
 
 #include <types.h>
 #include <soc/gpio.h>
@@ -29,4 +29,4 @@ struct soc_amd_i2c_save {
 
 void sb_reset_i2c_slaves(void);
 
-#endif /* __STONEYRIDGE_I2C_H__ */
+#endif /* AMD_STONEYRIDGE_I2C_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 8056287d4f..432888028a 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __SOC_STONEYRIDGE_IOMAP_H__
-#define __SOC_STONEYRIDGE_IOMAP_H__
+#ifndef AMD_STONEYRIDGE_IOMAP_H
+#define AMD_STONEYRIDGE_IOMAP_H
 
 /* MMIO Ranges */
 #define PSP_MAILBOX_BAR3_BASE		0xf0a00000
@@ -51,4 +51,4 @@
 #define BIOSRAM_UMA_SIZE		0xf4 /* 4 bytes */
 #define BIOSRAM_UMA_BASE		0xf8 /* 8 bytes */
 
-#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */
+#endif /* AMD_STONEYRIDGE_IOMAP_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 3b5fd22969..d00f5660d7 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
-#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
+#ifndef AMD_STONEYRIDGE_NORTHBRIDGE_H
+#define AMD_STONEYRIDGE_NORTHBRIDGE_H
 
 #include <device/device.h>
 #include <types.h>
@@ -89,4 +89,4 @@ void fam15_finalize(void *chip_info);
 void set_warm_reset_flag(void);
 int is_warm_reset(void);
 
-#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
+#endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
index 03a12336f7..6af657feb3 100644
--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
-#define __PI_STONEYRIDGE_PCI_DEVS_H__
+#ifndef AMD_STONEYRIDGE_PCI_DEVS_H
+#define AMD_STONEYRIDGE_PCI_DEVS_H
 
 #include <device/pci_def.h>
 #include <amdblocks/pci_devs.h>
@@ -201,4 +201,4 @@
 #define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
 #define SOC_SD_DEV		_SOC_DEV(SD_DEV, SD_FUNC)
 
-#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
+#endif /* AMD_STONEYRIDGE_PCI_DEVS_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h
index 6dc0b721a7..1cbaeec831 100644
--- a/src/soc/amd/stoneyridge/include/soc/romstage.h
+++ b/src/soc/amd/stoneyridge/include/soc/romstage.h
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __STONEYRIDGE_ROMSTAGE_H__
-#define __STONEYRIDGE_ROMSTAGE_H__
+#ifndef AMD_STONEYRIDGE_ROMSTAGE_H
+#define AMD_STONEYRIDGE_ROMSTAGE_H
 
 void mainboard_romstage_entry_s3(int s3_resume);
 
-#endif /* __STONEYRIDGE_ROMSTAGE_H__ */
+#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 15bba0fd9b..60a91d087a 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
-#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
+#ifndef AMD_STONEYRIDGE_SMI_H
+#define AMD_STONEYRIDGE_SMI_H
 
 #define SMI_GEVENTS			24
 #define SCIMAPS				58
@@ -218,4 +218,4 @@ void disable_gevent_smi(uint8_t gevent);
 void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
 void soc_route_sci(uint8_t event);
 
-#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
+#endif /* AMD_STONEYRIDGE_SMI_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 85df0b3b3a..cbd9caad95 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __STONEYRIDGE_H__
-#define __STONEYRIDGE_H__
+#ifndef AMD_STONEYRIDGE_SOUTHBRIDGE_H
+#define AMD_STONEYRIDGE_SOUTHBRIDGE_H
 
 #include <types.h>
 #include <device/device.h>
@@ -349,4 +349,4 @@ void i2c_soc_early_init(void);
 /* Initialize all the i2c buses that are not marked with early init. */
 void i2c_soc_init(void);
 
-#endif /* __STONEYRIDGE_H__ */
+#endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */