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authorDavid Hendricks <dhendrix@chromium.org>2013-01-31 17:22:50 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-01 06:16:23 +0100
commitea60473b9dea41571e1eac9afe93f712d66e557a (patch)
treea6d05a8fc52aaed38c48f350b84223b3f3870aee
parentd51557ade2a9f29cbb4e0f38d5a4920b42486168 (diff)
downloadcoreboot-ea60473b9dea41571e1eac9afe93f712d66e557a.tar.xz
exynos5250: #define the dram controller interleaving size
Change-Id: Iab184aa85be68b6ca5107d278d2fe821e5b2e611 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2255 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/cpu/samsung/exynos5250/dmc.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h
index b778e099d8..9b1f29305d 100644
--- a/src/cpu/samsung/exynos5250/dmc.h
+++ b/src/cpu/samsung/exynos5250/dmc.h
@@ -175,6 +175,8 @@ enum mem_manuf {
MEM_MANUF_COUNT = 2, // fancy that.
};
+#define DMC_INTERLEAVE_SIZE 0x1f
+
/* CONCONTROL register fields */
#define CONCONTROL_DFI_INIT_START_SHIFT 28
#define CONCONTROL_RD_FETCH_SHIFT 12