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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-09-26 13:56:24 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-03 20:24:42 +0000 |
| commit | ed3e6b8b946e0c5fbc417551750da67c284eaf8b (patch) | |
| tree | d91520a8122ca71345e53427817e9c78accdc768 | |
| parent | 5d11cc9d7e0ee016d6b6c540d010b212291d61cd (diff) | |
| download | coreboot-ed3e6b8b946e0c5fbc417551750da67c284eaf8b.tar.xz | |
soc/intel/cannonlake: Disable CPU ratio override
Disable CPU Ratio override as input to FSP Memory init.
Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index a9ad1d804e..1775cae779 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -86,6 +86,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable Cpu Ratio Override temporary. */ + m_cfg->CpuRatio = 0; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |