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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-03 03:05:17 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-11 18:48:38 +0100 |
| commit | ed85f614b06826721fdaf82df6cc049c4e35815a (patch) | |
| tree | 9752fd3dd2a531c4999af6287e88a7cf667b7a6a | |
| parent | 6116f369e98afef29e284c6148414d8c5832689d (diff) | |
| download | coreboot-ed85f614b06826721fdaf82df6cc049c4e35815a.tar.xz | |
nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch
Change-Id: I4497b0be6ed6c90dbb31e89013feed8ff5ff9071
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13885
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index b8d89fe675..f0e670b473 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1146,6 +1146,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, uint8_t lane; uint8_t nibble; uint8_t mem_clk; + uint16_t min_mem_clk; uint16_t initial_seed; uint8_t train_both_nibbles; uint16_t current_total_delay[MAX_BYTE_LANES]; @@ -1163,6 +1164,8 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, print_debug_dqs("\nTrainRcvEn: Node", pDCTstat->Node_ID, 0); print_debug_dqs("TrainRcvEn: Pass", Pass, 0); + min_mem_clk = mctGet_NVbits(NV_MIN_MEMCLK); + train_both_nibbles = 0; if (pDCTstat->Dimmx4Present) if (is_fam15h()) @@ -1274,7 +1277,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Adjust seed for the minimum platform supported frequency */ initial_seed = (uint16_t) (((((uint64_t) initial_seed) * - fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); + fam15h_freq_tab[mem_clk] * 100) / (min_mem_clk * 100))); for (lane = 0; lane < MAX_BYTE_LANES; lane++) { uint16_t wl_pass1_delay; @@ -1304,7 +1307,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < MAX_BYTE_LANES; lane++) { seed_prescaling = current_total_delay[lane] - register_delay - 0x20; - seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); + seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (min_mem_clk * 100))); } } |