diff options
author | Aaron Durbin <adurbin@chromium.org> | 2014-07-10 15:05:13 -0500 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-05 17:31:26 +0100 |
commit | eeacf74a7ce9f3302d813287e6409d660da43958 (patch) | |
tree | 665f7335f643a95dfab1c2e64bfcd95bad561970 | |
parent | 5626d8f59a4a70da4724e778a38e0fe6847fa5d8 (diff) | |
download | coreboot-eeacf74a7ce9f3302d813287e6409d660da43958.tar.xz |
t132: Enable cbmem console support
Enabled CBMEM support for t132 platforms. Some of the existing
code is moved around to avoid dependencies in the other stages
that need it.
BUG=None
BRANCH=None
TEST=Built and booted a rush with cbmem support.
Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207163
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b
Reviewed-on: http://review.coreboot.org/8589
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
-rw-r--r-- | src/soc/nvidia/tegra132/Kconfig | 4 | ||||
-rw-r--r-- | src/soc/nvidia/tegra132/Makefile.inc | 2 | ||||
-rw-r--r-- | src/soc/nvidia/tegra132/addressmap.c | 52 | ||||
-rw-r--r-- | src/soc/nvidia/tegra132/cbmem.c | 10 | ||||
-rw-r--r-- | src/soc/nvidia/tegra132/include/soc/addressmap.h | 4 | ||||
-rw-r--r-- | src/soc/nvidia/tegra132/romstage.c | 6 | ||||
-rw-r--r-- | src/soc/nvidia/tegra132/sdram.c | 26 | ||||
-rw-r--r-- | src/soc/nvidia/tegra132/sdram.h | 2 |
8 files changed, 76 insertions, 30 deletions
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 761685abc9..4dcf26f09c 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -83,4 +83,8 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00016000 +config CONSOLE_PRERAM_BUFFER_BASE + hex "memory address of the CBMEM console buffer" + default 0x40004020 + endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 252f1a22dd..5bbeefa097 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -17,6 +17,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif romstage-y += romstage_asm.S +romstage-y += addressmap.c romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += timer.c @@ -35,6 +36,7 @@ romstage-y += ../tegra/i2c.c romstage-y += ../tegra/pinmux.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += addressmap.c ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += timer.c diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c new file mode 100644 index 0000000000..92a7d76f65 --- /dev/null +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/io.h> +#include <stdlib.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include "mc.h" +#include "sdram.h" + +/* returns total amount of DRAM (in MB) from memory controller registers */ +int sdram_size_mb(void) +{ + struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE; + static int total_size = 0; + + if (total_size) + return total_size; + + /* + * This obtains memory size from the External Memory Aperture + * Configuration register. Nvidia confirmed that it is safe to assume + * this value represents the total physical DRAM size. + */ + total_size = (read32(&mc->emem_cfg) >> MC_EMEM_CFG_SIZE_MB_SHIFT) & + MC_EMEM_CFG_SIZE_MB_MASK; + + printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size); + return total_size; +} + +uintptr_t sdram_max_addressable_mb(void) +{ + return MIN((CONFIG_SYS_SDRAM_BASE/MiB) + sdram_size_mb(), 4096); +} diff --git a/src/soc/nvidia/tegra132/cbmem.c b/src/soc/nvidia/tegra132/cbmem.c index 495fcbae44..136d3eac89 100644 --- a/src/soc/nvidia/tegra132/cbmem.c +++ b/src/soc/nvidia/tegra132/cbmem.c @@ -18,9 +18,15 @@ */ #include <cbmem.h> +#include <soc/display.h> +#include <soc/addressmap.h> + +#define MTS_SIZE_MB 128 void *cbmem_top(void) { -/* TODO: update with real cbmem_top function. */ - return NULL; + /* FIXME(adurbin): use carveout registers properly. */ + const uintptr_t reserve = FB_SIZE_MB + MTS_SIZE_MB; + + return (void *)((sdram_max_addressable_mb() - reserve) << 20UL); } diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index d9d970a809..021a523f0d 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -22,6 +22,7 @@ #define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ #include <stddef.h> +#include <stdint.h> enum { TEGRA_SRAM_BASE = 0x40000000, @@ -80,4 +81,7 @@ enum { TEGRA_I2C_BASE_COUNT = 6, }; +int sdram_size_mb(void); +uintptr_t sdram_max_addressable_mb(void); + #endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 1d6acca5d0..e7e545d002 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -19,6 +19,8 @@ #include <arch/stages.h> #include <cbfs.h> +#include <cbmem.h> +#include <console/cbmem_console.h> #include <console/console.h> #include <arch/exception.h> @@ -39,6 +41,8 @@ void romstage(void) sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); + cbmem_initialize(); + ccplex_cpu_prepare(); printk(BIOS_INFO, "T132 romstage: cpu prepare done\n"); @@ -48,6 +52,8 @@ void romstage(void) entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage"); + cbmemc_reinit(); + ccplex_cpu_start(entry); while (1); diff --git a/src/soc/nvidia/tegra132/sdram.c b/src/soc/nvidia/tegra132/sdram.c index 4e1f7ecfe8..0b1edf10f9 100644 --- a/src/soc/nvidia/tegra132/sdram.c +++ b/src/soc/nvidia/tegra132/sdram.c @@ -619,29 +619,3 @@ uint32_t sdram_get_ram_code(void) PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } - -/* returns total amount of DRAM (in MB) from memory controller registers */ -int sdram_size_mb(void) -{ - struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE; - static int total_size = 0; - - if (total_size) - return total_size; - - /* - * This obtains memory size from the External Memory Aperture - * Configuration register. Nvidia confirmed that it is safe to assume - * this value represents the total physical DRAM size. - */ - total_size = (read32(&mc->emem_cfg) >> - MC_EMEM_CFG_SIZE_MB_SHIFT) & MC_EMEM_CFG_SIZE_MB_MASK; - - printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size); - return total_size; -} - -uintptr_t sdram_max_addressable_mb(void) -{ - return MIN((CONFIG_SYS_SDRAM_BASE/MiB) + sdram_size_mb(), 4096); -} diff --git a/src/soc/nvidia/tegra132/sdram.h b/src/soc/nvidia/tegra132/sdram.h index ab6bf0fd18..7684eb86d4 100644 --- a/src/soc/nvidia/tegra132/sdram.h +++ b/src/soc/nvidia/tegra132/sdram.h @@ -24,8 +24,6 @@ uint32_t sdram_get_ram_code(void); void sdram_init(const struct sdram_params *param); -int sdram_size_mb(void); -uintptr_t sdram_max_addressable_mb(void); /* Save params to PMC scratch registers for use by BootROM on LP0 resume. */ void sdram_lp0_save_params(const struct sdram_params *sdram); |