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authorNico Huber <nico.h@gmx.de>2019-11-04 16:21:25 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-05 15:24:15 +0000
commitef63c32b5843c8b585804aa7ba37a3e7da2b7b1a (patch)
treeac11228530b414523164ff193046ebf219febbd1
parent6b5bf407deb52a900ef0a8a0b99f853be1eb7e82 (diff)
downloadcoreboot-ef63c32b5843c8b585804aa7ba37a3e7da2b7b1a.tar.xz
arch/riscv: Don't link `stages.c` into ramstage
It's superseded by `ramstage.S`. Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/arch/riscv/Makefile.inc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 0039fab180..16f160e8db 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -140,7 +140,6 @@ ramstage-y += fp_asm.S
ramstage-y += misaligned.c
ramstage-y += sbi.c
ramstage-y += virtual_memory.c
-ramstage-y += stages.c
ramstage-y += misc.c
ramstage-y += smp.c
ramstage-y += boot.c