diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2018-01-24 13:17:51 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-26 17:25:41 +0000 |
| commit | efea957ed68b1e3f345b1bc8d1dc4cac30824325 (patch) | |
| tree | 1f64c6dff235fa6f9f0157c54d1bb4228afc24b3 | |
| parent | 8a1f095e50e068e42d378f47c79467e7b6295b7b (diff) | |
| download | coreboot-efea957ed68b1e3f345b1bc8d1dc4cac30824325.tar.xz | |
mb/google/poppy/variants/soraka: Configure unused pins as NC
This change configures unused pins as not connected.
Change-Id: I6779d9fba73da8fb2faa08ad5d2236b813105720
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23416
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/gpio.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 50bac4bade..0e24bb76dd 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -127,10 +127,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* C7 : SM1DATA ==> NC */ PAD_CFG_NC(GPP_C7), - /* C8 : UART0_RXD ==> FP_INT */ - PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), - /* C9 : UART0_TXD ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_C9, 0, DEEP), + /* C8 : UART0_RXD ==> NC */ + PAD_CFG_NC(GPP_C8), + /* C9 : UART0_TXD ==> NC */ + PAD_CFG_NC(GPP_C9), /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ @@ -170,10 +170,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_D3), /* D4 : FASHTRIG ==> NC */ PAD_CFG_NC(GPP_D4), - /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), - /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_CFG_NC(GPP_D5), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_CFG_NC(GPP_D6), /* D7 : ISH_I2C1_SDA ==> NC */ PAD_CFG_NC(GPP_D7), /* D8 : ISH_I2C1_SCL ==> NC */ @@ -258,7 +258,7 @@ static const struct pad_config gpio_table[] = { /* E23 : DDPD_CTRLDATA ==> NC */ PAD_CFG_NC(GPP_E23), - /* The next 4 pads are for bit banging the amplifiers, default to I2S */ + /* The next 3 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */ |