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authorSubrata Banik <subrata.banik@intel.com>2018-05-17 15:57:43 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-06-06 06:17:09 +0000
commitf513cebd8b966c15e3c8abcd2d0f540607ea5964 (patch)
treed1a24c10038bd8471bc339eaf4ea818d0fa1241d
parent19cd07f2a015b419e55ee998ea67fd2e1ff7b2ff (diff)
downloadcoreboot-f513cebd8b966c15e3c8abcd2d0f540607ea5964.tar.xz
soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNL
This patch creates a glue layer between SOC and common block IPs in terms of PCH. All common IP blocks now can be selected based on SOC_INTEL_COMMON_PCH_BASE config option. BUG=none BRANCH=b:78109109 TEST=Build and boot Cannonlake RVP and EVE. Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/cannonlake/Kconfig23
-rw-r--r--src/soc/intel/skylake/Kconfig24
2 files changed, 2 insertions, 45 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 3b6837448d..f50d9f2bd6 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -48,32 +48,11 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
- select SOC_INTEL_COMMON_BLOCK_CSE
- select SOC_INTEL_COMMON_BLOCK_DSP
- select SOC_INTEL_COMMON_BLOCK_EBDA
- select SOC_INTEL_COMMON_BLOCK_FAST_SPI
- select SOC_INTEL_COMMON_BLOCK_GPIO
- select SOC_INTEL_COMMON_BLOCK_GRAPHICS
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
- select SOC_INTEL_COMMON_BLOCK_ITSS
- select SOC_INTEL_COMMON_BLOCK_I2C
- select SOC_INTEL_COMMON_BLOCK_LPC
- select SOC_INTEL_COMMON_BLOCK_LPSS
- select SOC_INTEL_COMMON_BLOCK_P2SB
- select SOC_INTEL_COMMON_BLOCK_PCR
- select SOC_INTEL_COMMON_BLOCK_PMC
- select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
- select SOC_INTEL_COMMON_BLOCK_SATA
- select SOC_INTEL_COMMON_BLOCK_SCS
- select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
- select SOC_INTEL_COMMON_BLOCK_SPI
- select SOC_INTEL_COMMON_BLOCK_TIMER
- select SOC_INTEL_COMMON_BLOCK_UART
- select SOC_INTEL_COMMON_BLOCK_XDCI
- select SOC_INTEL_COMMON_BLOCK_XHCI
+ select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SSE2
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index c275b5db45..bfaa19f5d6 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -58,37 +58,15 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
- select SOC_INTEL_COMMON_BLOCK_CSE
- select SOC_INTEL_COMMON_BLOCK_DSP
- select SOC_INTEL_COMMON_BLOCK_EBDA
- select SOC_INTEL_COMMON_BLOCK_FAST_SPI
- select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
- select SOC_INTEL_COMMON_BLOCK_GRAPHICS
select SOC_INTEL_COMMON_BLOCK_GSPI
- select SOC_INTEL_COMMON_BLOCK_I2C
- select SOC_INTEL_COMMON_BLOCK_ITSS
- select SOC_INTEL_COMMON_BLOCK_LPC
- select SOC_INTEL_COMMON_BLOCK_LPSS
- select SOC_INTEL_COMMON_BLOCK_P2SB
- select SOC_INTEL_COMMON_BLOCK_PCIE
- select SOC_INTEL_COMMON_BLOCK_PCR
- select SOC_INTEL_COMMON_BLOCK_PMC
- select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
- select SOC_INTEL_COMMON_BLOCK_SATA
- select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_SGX
- select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
- select SOC_INTEL_COMMON_BLOCK_SPI
- select SOC_INTEL_COMMON_BLOCK_TIMER
- select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_VMX
- select SOC_INTEL_COMMON_BLOCK_XDCI
- select SOC_INTEL_COMMON_BLOCK_XHCI
+ select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SSE2