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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-20 14:21:53 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-21 20:30:30 +0100
commitf7d4f73053f0c26bfe411a9f3ef86f98389538b5 (patch)
treeba887ea31ce6b3579d08328635038583a4451917
parenta4d81809137b8b53903303b201c2d1bfbc615143 (diff)
downloadcoreboot-f7d4f73053f0c26bfe411a9f3ef86f98389538b5.tar.xz
nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
Under certain conditions (training abort) BlockRxDqsLock could remain set in violation of the BKDG. Ensure BlockRxDqsLock is reset to 0 after a lane training abort. Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b Reviewed-on: https://review.coreboot.org/14144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 15b5ea4fcb..5d75fb0392 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1725,6 +1725,12 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
"Training for receiver %d on DCT %d aborted\n",
__func__, lane, Receiver, dct);
}
+
+ /* Restore BlockRxDqsLock setting to normal operation in preparation for retraining */
+ dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8));
+ dword &= ~(0x1 << 8); /* BlockRxDqsLock = 0 */
+ Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword);
+
break;
}