diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-24 17:49:35 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-26 22:39:35 +0200 |
| commit | f8a4f41d48acc9ecffc9d74185fad0cb8651f4da (patch) | |
| tree | db4d7e01888b30d72af72cad081098d93b9cc719 | |
| parent | 606b8bccb53e5bbc840d29657faaf333eff51e38 (diff) | |
| download | coreboot-f8a4f41d48acc9ecffc9d74185fad0cb8651f4da.tar.xz | |
nb/x4x/gma.c: Remove writes to DP, FDI registers
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17111
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/northbridge/intel/x4x/gma.c | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 749a7c827a..62e28aafc4 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -74,12 +74,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00040000; - vga_gr_write(0x18, 0); @@ -210,10 +204,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", @@ -228,12 +218,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", @@ -305,13 +289,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE |