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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-06-10 19:35:15 +0200
committerMartin Roth <martinroth@google.com>2016-06-12 12:41:48 +0200
commitf934efc9f8e2fe0791f47e7088301199629827b1 (patch)
tree55c71ccea64a053f59e96d81baf307a225d77045
parenta9067c6ec0b4a197d6eaa7ef3ab24c7b9e1e3826 (diff)
downloadcoreboot-f934efc9f8e2fe0791f47e7088301199629827b1.tar.xz
arch/riscv: Add misc.c to bootblock/romstage to get udelay()
The uart8250mem driver needs it. Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/arch/riscv/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 6784d9bb48..4521dcbba6 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -34,6 +34,7 @@ bootblock-y += trap_handler.c
bootblock-y += virtual_memory.c
bootblock-y += boot.c
bootblock-y += rom_media.c
+bootblock-y += misc.c
bootblock-y += \
$(top)/src/lib/memchr.c \
$(top)/src/lib/memcmp.c \
@@ -57,6 +58,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
romstage-y += boot.c
romstage-y += stages.c
romstage-y += rom_media.c
+romstage-y += misc.c
romstage-y += \
$(top)/src/lib/memchr.c \
$(top)/src/lib/memcmp.c \