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authorLijian Zhao <lijian.zhao@intel.com>2019-04-11 00:50:39 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-04-19 01:39:15 +0000
commitfc5a3c949dd7ea2aa1d495fb59bbca32e96c0ef6 (patch)
treea6f7acefec0b1f91185617f456ab2fbf7eea7d25
parent10ea93c3341dcae75b29e7dd049a948260d0f190 (diff)
downloadcoreboot-fc5a3c949dd7ea2aa1d495fb59bbca32e96c0ef6.tar.xz
mb/google/sarien: Update SMBIOS type17
Match SMBIOS type 17 device locator with motherboard silk screen,using "DIMM-A" and "DIMM-B" instead of "Channel-0-DIMM-0" and "Chaneel-1-DIMM-0". TEST=Boot up with sarien platform and run dmidecode to check SMBIOS type 17 have expected output. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie2125c0381bd24d96f725f68cde93a53da8c94c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--src/mainboard/google/sarien/ramstage.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index 96321f8d49..d8d1c9dbe3 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -14,11 +14,31 @@
*/
#include <arch/acpi.h>
+#include <smbios.h>
#include <soc/gpio.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+/* mainboard silk screen shows DIMM-A and DIMM-B */
+void smbios_fill_dimm_locator(const struct dimm_info *dimm,
+ struct smbios_type17 *t)
+{
+ switch (dimm->channel_num) {
+ case 0:
+ t->device_locator = smbios_add_string(t->eos, "DIMM-A");
+ break;
+ case 1:
+ t->device_locator = smbios_add_string(t->eos, "DIMM-B");
+ break;
+ default:
+ t->device_locator = smbios_add_string(t->eos, "UNKNOWN");
+ break;
+ }
+}
+#endif
+
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
const struct pad_config *gpio_table;