diff options
| author | Mariusz Szafranski <mariuszx.szafranski@intel.com> | 2017-09-12 14:15:35 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-15 02:42:07 +0000 |
| commit | 025d819ee1d2f0e16af38d68fd7bb50c743b4960 (patch) | |
| tree | 1c2e88fd820e9d0797aa00b2e5f81b19e42eb481 | |
| parent | e69a9c75816dd3cd6a9af50a09eb090ea00cfed4 (diff) | |
| download | coreboot-025d819ee1d2f0e16af38d68fd7bb50c743b4960.tar.xz | |
MAINTAINERS: Add INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
Add Intel FSP Atom C3000 SoC ("Denverton" and "Denverton-NS")
and Harcuvar CRB to the list.
Change-Id: I1c4bfd0900e8d425b95b5ef6c541b1e988846667
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/21515
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
| -rw-r--r-- | MAINTAINERS | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 76510cca09..56218a2bee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -207,6 +207,15 @@ F: src/vendorcode/intel/fsp1_0/ivybridge_i89xx F: src/mainboard/intel/cougar_canyon2/ F: src/mainboard/intel/stargo2/ +INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB +M: SweeHeng Wong <swee.heng.wong@intel.com> +M: Vanessa Eusebio <vanessa.f.eusebio@intel.com> +M: Fei Wang <fei.z.wang@intel.com> +S: Supported +F: src/mainboard/intel/harcuvar/ +F: src/soc/intel/denverton_ns/ +F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/ + FSP 1.0 RANGELEY & CRB M: David Guckian <david.guckian@intel.com> M: Fei Wang <fei.z.wang@intel.com> |