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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-06 22:10:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-08 07:26:07 +0000 |
| commit | 05f996d433ef91e699503e1ef679f6cafdf00d3b (patch) | |
| tree | 88d32161943c2876d5bf1a70497211f7d6fcf475 | |
| parent | 32b13131c1d4ed874930de886c0b097e91993d37 (diff) | |
| download | coreboot-05f996d433ef91e699503e1ef679f6cafdf00d3b.tar.xz | |
nb/intel/haswell/acpi: Fix host bridge registers
The host bridge register definitions haven't changed from Sandy Bridge
to Haswell, according to the datasheets. However, coreboot's ACPI code
is not the same. Looks like Haswell values are wrong, so correct them.
Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/hostbridge.asl | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index dd4b79a6cf..0f2ed1625b 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -16,24 +15,24 @@ Device (MCHC) Offset (0x40), // EPBAR EPEN, 1, // Enable , 11, // - EPBR, 24, // EPBAR + EPBR, 27, // EPBAR Offset (0x48), // MCHBAR MHEN, 1, // Enable - , 13, // - MHBR, 22, // MCHBAR + , 14, // + MHBR, 24, // MCHBAR Offset (0x54), DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size , 23, // - PXBR, 10, // PCIe BAR + PXBR, 13, // PCIe BAR Offset (0x68), // DMIBAR DMEN, 1, // Enable , 11, // - DMBR, 24, // DMIBAR + DMBR, 27, // DMIBAR Offset (0x70), // ME Base Address MEBA, 64, |