diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 22:51:33 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-09 20:46:50 +0000 |
commit | 060b8ad7a324d8aada887133fd1222a9d66c678b (patch) | |
tree | e7c04ddce798a38205b7c5edd507d6fc9baabfef | |
parent | ccf99a39d202535ceaa19493f7f762116efc8d50 (diff) | |
download | coreboot-060b8ad7a324d8aada887133fd1222a9d66c678b.tar.xz |
soc/amd/cezanne: add empty CPU driver
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
-rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/amd/cezanne/cpu.c | 24 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 7f59ef495e..9a59d5dabc 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += romstage.c romstage-y += uart.c ramstage-y += chip.c +ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c new file mode 100644 index 0000000000..3e0a7dbbd8 --- /dev/null +++ b/src/soc/amd/cezanne/cpu.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <soc/cpu.h> + +static void zen_2_3_init(struct device *dev) +{ +} + +static struct device_operations cpu_dev_ops = { + .init = zen_2_3_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, CEZANNE_A0_CPUID}, + { 0, 0 }, +}; + +static const struct cpu_driver zen_2_3 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; |