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| author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2013-06-08 10:25:06 +0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-29 18:57:42 +0200 |
| commit | 0d8d482f6316885d7e553d9aeb538ce5bbd2fbba (patch) | |
| tree | 9fb17f68b76d5b04169a94eb9ab7e3e8dfa41968 | |
| parent | bc2c9efd56a1b7d5c9b97132423ac176b4d21b74 (diff) | |
| download | coreboot-0d8d482f6316885d7e553d9aeb538ce5bbd2fbba.tar.xz | |
AMD S3 resume: Add framwork to write bigger data
This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1]
Some AMD south bridge can write bigger data when saving S3 info.
In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size.
AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig'
and then can be overridden in the Kconfig for specific
southbridges that support larger size.
I have tested on AMD Parmer and Thatcher. We will release a new board
whose south bridge can transfer more than 4 bytes each time.
[1] http://review.coreboot.org/#/c/2306/
Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3413
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 11 | ||||
| -rw-r--r-- | src/southbridge/amd/Kconfig | 3 |
2 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 8a9ffeea63..6ba9212ab4 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -152,10 +152,16 @@ void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx) { msr_t msr_data; msr_data = rdmsr(idx); + +#if CONFIG_AMD_SB_SPI_TX_LEN >= 8 + flash->write(flash, *p_nvram_pos, 8, &msr_data); + *p_nvram_pos += 8; +#else flash->write(flash, *p_nvram_pos, 4, &msr_data.lo); *p_nvram_pos += 4; flash->write(flash, *p_nvram_pos, 4, &msr_data.hi); *p_nvram_pos += 4; +#endif } #endif @@ -264,10 +270,11 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) nvram_pos = 0; flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); - for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) { data = *(u32 *) (Data + nvram_pos); - flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); } + flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 20d557307a..42209ce7b2 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -18,3 +18,6 @@ source src/southbridge/amd/sr5650/Kconfig config SPI_FLASH bool default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA +config AMD_SB_SPI_TX_LEN + int + default 4 |