diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-06-20 17:26:21 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:18:22 +0000 |
| commit | 0fcd37172f22a55fecd5ae6752fc18218b88a8f3 (patch) | |
| tree | 760464e8fd493cfe65e3efd4a0920937db506ab5 | |
| parent | 0948b363b0568e70af2352566dee39e0df82d96d (diff) | |
| download | coreboot-0fcd37172f22a55fecd5ae6752fc18218b88a8f3.tar.xz | |
mb/kontron: Add Kontron mAL10 COMe module support
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.
Working:
- UART console and I2C on Kontron kempld;
- USB2/3
- Ethernet controller
- eMMC
- SATA
- PCIe ports
- IGD/DP
- SMBus
- HWM
Not tested:
- IGD/LVDS
- SDIO
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
Tested payloads:
- SeaBIOS
- Tianocore, UEFIPayload - without video, EFI-shell in console only
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
26 files changed, 961 insertions, 0 deletions
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d6aed22128..4b46b7ce02 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -76,6 +76,10 @@ The boards in this section are not real mainboards, but emulators. - [IceLake RVP](intel/icelake_rvp.md) - [KBLRVP11](intel/kblrvp11.md) +## Kontron + +- [mAL-10](kontron/mal10.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) diff --git a/Documentation/mainboard/kontron/mal10.md b/Documentation/mainboard/kontron/mal10.md new file mode 100644 index 0000000000..b2eefc3df2 --- /dev/null +++ b/Documentation/mainboard/kontron/mal10.md @@ -0,0 +1,106 @@ +# Kontron mAL10 Computer-on-Modules platform + +The Kontron [mAL10] COMe is a credit card sized Computer-on-Modules +platform based on the Intel Atom E3900 Series, Pentium and Celeron +processors. + +## Technology + +```eval_rst ++------------------+----------------------------------+ +| COMe Type | mini pin-out type 10 | ++------------------+----------------------------------+ +| SoC | Intel Atom x5-E3940 (4 core) | ++------------------+----------------------------------+ +| GPU | Intel HD Graphics 500 | ++------------------+----------------------------------+ +| Coprocessor | Intel TXE 3.0 | ++------------------+----------------------------------+ +| RAM | 8GB DDR3L | ++------------------+----------------------------------+ +| eMMC Flash | 32GB eMMC pSLC | ++------------------+----------------------------------+ +| USB3 | x2 | ++------------------+----------------------------------+ +| USB2 | x6 | ++------------------+----------------------------------+ +| SATA | x2 | ++------------------+----------------------------------+ +| LAN | Intel I210IT, I211AT | ++------------------+----------------------------------+ +| Super IO/EC | Kontron CPLD/EC | ++------------------+----------------------------------+ +| HWM | NCT7802 | ++------------------+----------------------------------+ +``` + +## Building coreboot + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.kontron_mal10 +make +``` +## Payloads +- SeaBIOS +- Tianocore +- Linux as payload + +## Flashing coreboot + +The SPI flash can be accessed internally using [flashrom]. +The following command is used to flash BIOS region. + +```bash +$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all +``` + +## Hardware Monitor + +The Nuvoton [NCT7802Y] is a hardware monitoring IC, capable of monitor critical +system parameters including power supply voltages, fan speeds, and temperatures. +The remote inputs can be connected to CPU/GPU thermal diode or any thermal diode +sensors and thermistor. + +- 6 temperature sensors; +- 5 voltage sensors; +- 3 fan speed sensors; +- 4 sets of temperature setting points. + +PECI is not supported by Apollo Lake Pentium/Celeron/Atom processors and the CPU +temperature value is taken from a thermal resistor (NTC) that is placed very +close to the CPU. + +## Known issues + +- Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 + Booting with the "CorebootPayload" [crashes]. +- Tianocore outputs video through an external GPU only. + +## Untested + +- IGD/LVDS +- SDIO + +## Tested and working + +- Kontron CPLD/EC (Serial ports, I2C port) +- NCT7802 [HWM](#Hardware Monitor) +- USB2/3 +- Gigabit Ethernet ports +- eMMC +- SATA +- PCIe ports +- IGD/DP + +## TODO +- Onboard audio (codec IDT 92HD73C1X5, currently disabled) +- S3 suspend/resume + +[mAL10]: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html +[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf +[flashrom]: https://flashrom.org/Flashrom +[NCT7802Y]: https://www.nuvoton.com/products/cloud-computing/hardware-monitors/desktop-server-series/nct7802y/?__locale=en +[crashes]: https://pastebin.com/cpCfrPCL diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig new file mode 100644 index 0000000000..1705b9109c --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig @@ -0,0 +1,58 @@ +if BOARD_KONTRON_COME_MAL10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select ONBOARD_VGA_IS_PRIMARY + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_CRB_TPM + select EC_KONTRON_KEMPLD + select DRIVERS_I2C_NCT7802Y + +config MAINBOARD_DIR + string + default "kontron/mal10" + +# TODO: Add a new carrier boards here +choice + prompt "Carrier board" + default BOARD_KONTRON_T10_TNI + help + This option sets the type of carrier board to be used with + the Kontron mAL10 COMe module. + +config BOARD_KONTRON_T10_TNI + bool "Kontron i-T10-TNIx" + help + By selecting this option, the target ROM image will be built for + the Kontron Ref.Carrier-i T10-TNI carrier board. + +endchoice + +config VARIANT_DIR + string + default "mal10" + +config CARRIER_DIR + string + default "t10-tni" if BOARD_KONTRON_T10_TNI + +config MAINBOARD_PART_NUMBER + string + default "COMe-mAL10" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "carriers/$(CONFIG_CARRIER_DIR)/overridetree.cb" + +endif diff --git a/src/mainboard/kontron/mal10/Kconfig.name b/src/mainboard/kontron/mal10/Kconfig.name new file mode 100644 index 0000000000..ac54165880 --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_KONTRON_COME_MAL10 + bool "COMe-mAL10" diff --git a/src/mainboard/kontron/mal10/Makefile.inc b/src/mainboard/kontron/mal10/Makefile.inc new file mode 100644 index 0000000000..885786fc55 --- /dev/null +++ b/src/mainboard/kontron/mal10/Makefile.inc @@ -0,0 +1,9 @@ +bootblock-y += bootblock.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += carriers/$(CARRIER_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/carriers/$(CARRIER_DIR)/include diff --git a/src/mainboard/kontron/mal10/acpi/dptf.asl b/src/mainboard/kontron/mal10/acpi/dptf.asl new file mode 100644 index 0000000000..240da453bd --- /dev/null +++ b/src/mainboard/kontron/mal10/acpi/dptf.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 10000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/kontron/mal10/board_info.txt b/src/mainboard/kontron/mal10/board_info.txt new file mode 100644 index 0000000000..d93d125911 --- /dev/null +++ b/src/mainboard/kontron/mal10/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/bootblock.c b/src/mainboard/kontron/mal10/bootblock.c new file mode 100644 index 0000000000..5c40e2dc6c --- /dev/null +++ b/src/mainboard/kontron/mal10/bootblock.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <intelblocks/lpc_lib.h> +#include <ec/kontron/kempld/kempld.h> +#include <variant/gpio.h> + +static void init_cpld(void) +{ + /* Set up LPC decoding for CPLD I/O port ranges */ + lpc_open_pmio_window(0x0A80, 2); + + /* Enable console serial ports */ + lpc_io_setup_comm_a_b(); + kempld_enable_uart_for_console(); +} + +void bootblock_mainboard_early_init(void) +{ + variant_early_gpio_configure(); + init_cpld(); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc new file mode 100644 index 0000000000..c291d45ebd --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += gpio.c diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt new file mode 100644 index 0000000000..2902dc4b85 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-Ref-Carrier-i-T10-TNI +Board URL: https://www.kontron.com/products/boards-and-standard-form-factors/com-express/starterkits-and-evaluation-boards/come-ref.carrier-i-t10-tni.html +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c new file mode 100644 index 0000000000..f1f93bf4fc --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/carrier/gpio.h" + +static const struct pad_config gpio_table[] = { + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_5, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_6, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_7, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_8, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_9, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_10, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_11, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_12, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_13, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_14, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_15, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_16, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_17, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPIO_18, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_19, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_20, DN_20K, DEEP, OFF, TxDRxE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_21, UP_20K, DEEP, OFF, TxDRxE, DRIVER), + /* GPIO_22 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_22, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_22, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_23 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_23, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE : PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_23, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_24 - GPIO (DW0: 0x40800102, DW1: 0x00027100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_24, UP_20K, DEEP, LEVEL, TxDRxE, DISPUPD, ACPI), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_24, + PAD_RESET(DEEP) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_SCI_IOS(GPIO_25, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), + PAD_CFG_NF(GPIO_26, NATIVE, DEEP, NF5), + PAD_CFG_GPI_SCI_IOS(GPIO_27, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), + PAD_CFG_GPIO_BIDIRECT(GPIO_28, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_29, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_30, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_31, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_32, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_33, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_34, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_35, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_36, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_37, DN_20K, DEEP, HIZCRx0, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_38, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_39, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_40, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_41, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_48, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_49, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPIO_62, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT_IOS(GPIO_63, 0, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_64, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_65, 0, NONE, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_66, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_67, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_68, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_69, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_70, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_71, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_72, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_73, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), + PAD_CFG_NF(TMS, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDI, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1), + PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDO, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, UP_20K, DEEP), + PAD_CFG_TERM_GPO(CNV_RGI_DT, 0, UP_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_188, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_189, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_190, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_191, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_192, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_193, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_194, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_195, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_197, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_198, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_199, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_200, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_201, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_202, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS0, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS2, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_RXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_TXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_CLK, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_PWRGOOD, NONE, DEEP, NF1), + PAD_CFG_NF(PMIC_RESET_B, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_213, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_214, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_215, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_STDBY, DN_20K, DEEP, NF1), + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_74, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_75, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_76, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_77, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_78, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_79, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_80, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_81, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_82, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_83, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_84, DN_20K, DEEP, NF2), + PAD_CFG_GPIO_HI_Z(GPIO_85, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_86, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_87, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_88, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_89, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_90, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_91, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_92, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_104, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_105, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_106, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_109, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_110, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_111, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_112, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_113, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_116, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_117, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_118, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_119, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_120, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_121, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_122, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_123, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_124, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_125, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_126, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_127, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_128, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_129, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_130, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_131, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_132, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_133, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_134, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_135, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_137, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_138, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_139, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_146, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_147, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_148, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_149, DN_20K, DEEP, NF3), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_150, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_151, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_152, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_153, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_154, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_155, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPIO_209, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_AC_PRESENT, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_BATLOW_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PLTRST_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PWRBTN_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S3_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S4_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SUSCLK, NONE, DEEP, NF1), + PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUS_STAT_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUSPWRDNACK, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_205, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_206, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_207, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_208, NONE, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_156, DN_20K, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_166, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_167, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_168, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_169, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_170, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_171, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_176, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_177, UP_20K, DEEP, EDGE_BOTH, TxDRxE, DRIVER), + PAD_CFG_NF_IOSSTATE(GPIO_178, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0), + PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void carrier_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h b/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h new file mode 100644 index 0000000000..9c9c8edc83 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef T10_TNI_CFG_GPIO_H +#define T10_TNI_CFG_GPIO_H + +#include <gpio.h> +#include <stddef.h> + +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT_IOS +#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#endif + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void carrier_gpio_configure(void); + +#endif /* T10_TNI_CFG_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb new file mode 100644 index 0000000000..9248c0c21c --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Override USB port configuration + register "usb_config_override" = "1" + # USB 2.0 + register "usb2_port[0]" = "PORT_EN(OC1)" + register "usb2_port[1]" = "PORT_EN(OC1)" + register "usb2_port[2]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC1)" + register "usb2_port[4]" = "PORT_EN(OC1)" + register "usb2_port[5]" = "PORT_EN(OC1)" + register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + # USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + register "usb3_port[1]" = "PORT_EN(OC0)" + + device domain 0 on + device pci 0e.0 off end # TODO: Audio + device pci 13.0 on # PCIe-A 1 (Root Port 2) + register "pcie_rp_clkreq_pin[2]" = "0" + end + device pci 13.1 on # PCIe-A 2 (Root Port 3) + register "pcie_rp_clkreq_pin[3]" = "0" + end + device pci 13.2 on # PCIe-A 3 (Root Port 4) + register "pcie_rp_clkreq_pin[4]" = "0" + end + device pci 13.3 on # PCIe-A 4 (Root Port 5) + register "pcie_rp_clkreq_pin[5]" = "0" + end + device pci 14.0 on # PCIe-B 1 (Root Port 0) + register "pcie_rp_clkreq_pin[0]" = "1" + end + end +end diff --git a/src/mainboard/kontron/mal10/cmos.default b/src/mainboard/kontron/mal10/cmos.default new file mode 100644 index 0000000000..55cac796c6 --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.default @@ -0,0 +1,6 @@ +baud_rate = 115200 +debug_level = Info +power_on_after_fail = Enable +boot_devices = (hd0,0);(hd1,0) +boot_default = 0xff +cmos_defaults_loaded = No diff --git a/src/mainboard/kontron/mal10/cmos.layout b/src/mainboard/kontron/mal10/cmos.layout new file mode 100644 index 0000000000..cc5359f4b7 --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.layout @@ -0,0 +1,55 @@ +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 +441 1 e 2 ethernet2 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/kontron/mal10/dsdt.asl b/src/mainboard/kontron/mal10/dsdt.asl new file mode 100644 index 0000000000..78d2c285a5 --- /dev/null +++ b/src/mainboard/kontron/mal10/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB) + { + Device(PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + } + #include "acpi/dptf.asl" + #include <soc/intel/apollolake/acpi/dptf.asl> + #include <soc/intel/common/acpi/dptf/dptf.asl> + } +} diff --git a/src/mainboard/kontron/mal10/mal10.fmd b/src/mainboard/kontron/mal10/mal10.fmd new file mode 100644 index 0000000000..21d780a066 --- /dev/null +++ b/src/mainboard/kontron/mal10/mal10.fmd @@ -0,0 +1,21 @@ +FLASH 16M { + SI_DESC 0x1000 + SI_BIOS 0xefe000 { + IFWI 0x2ff000 + OBB 0xbff000 { + FMAP 0x1000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 + } + CONSOLE 0x20000 + COREBOOT(CBFS) + BIOS_UNUSABLE 0x40000 + } + } + SI_DEVICEEXT 0x101000 { + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 + } +} diff --git a/src/mainboard/kontron/mal10/ramstage.c b/src/mainboard/kontron/mal10/ramstage.c new file mode 100644 index 0000000000..48194e6848 --- /dev/null +++ b/src/mainboard/kontron/mal10/ramstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <carrier/gpio.h> +#include <stddef.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + carrier_gpio_configure(); + + /* + * CPU Power Management Configuration correspond to the BIOS Setup menu settings + * in the AMI UEFI v112. + * TODO: move these FSP options to device tree + */ + silconfig->EnableCx = 1; /* Enable CPU power states */ + silconfig->C1e = 1; /* enable Enhanced C-states */ + /* + * Attention! Do not change PkgCStateLimit! This causes spikes in the power + * consumption of the SoC when the system comes out of power saving mode, and + * voltage sagging at the output of DC-DC converters on the COMe module. In the + * AMI BIOS Setup shows this parameter, but does not allow changing it. + */ + silconfig->PkgCStateLimit = 0; /* Max Pkg Cstate : PkgC0C1 */ + silconfig->MaxCoreCState = 3; /* Max Core C-State : C6 */ + silconfig->CStateAutoDemotion = 0; /* Disable C1 and C3 Auto-demotion */ + silconfig->CStateUnDemotion = 0; /* Disable C1 and C3 Un-demotion */ + silconfig->PkgCStateDemotion = 1; /* enable package Cstate demotion */ + silconfig->PkgCStateUnDemotion = 1; /* enable package Cstate undemotion */ + silconfig->PmSupport = 1; /* GT PM Support */ + silconfig->EnableRenderStandby = 1; /* enable render standby */ + silconfig->LPSS_S0ixEnable = 1; /* LPSS IOSF PMCTL S0ix Enable */ + silconfig->InitS3Cpu = 1; /* initialize CPU during S3 resume */ + + /* Override High Precision Timer options */ + silconfig->HpetBdfValid = 1; + silconfig->HpetBusNumber = 0xFA; + silconfig->HpetDeviceNumber = 0x0F; + silconfig->HpetFunctionNumber = 0; + + /* Override APIC options */ + silconfig->IoApicId = 1; + silconfig->IoApicBdfValid = 1; + silconfig->IoApicBusNumber = 0xFA; + silconfig->IoApicDeviceNumber = 0x1F; + silconfig->IoApicFunctionNumber = 0; +} diff --git a/src/mainboard/kontron/mal10/romstage.c b/src/mainboard/kontron/mal10/romstage.c new file mode 100644 index 0000000000..9f1d7eb87d --- /dev/null +++ b/src/mainboard/kontron/mal10/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <soc/romstage.h> +#include <FspmUpd.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mupd->FspmConfig.Package = 0; + mupd->FspmConfig.Profile = 0x19; + mupd->FspmConfig.MemoryDown = 0; + mupd->FspmConfig.DDR3LPageSize = 2; + mupd->FspmConfig.DualRankSupportEnable = 0; + mupd->FspmConfig.RmtMode = 0; + mupd->FspmConfig.MemorySizeLimit = 0; + mupd->FspmConfig.DIMM0SPDAddress = 0xA0; + mupd->FspmConfig.DIMM1SPDAddress = 0xA4; + + mupd->FspmConfig.RmtCheckRun = 1; + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0; + mupd->FspmConfig.EnhancePort8xhDecoding = 1; + + mupd->FspmConfig.MsgLevelMask = 0; + mupd->FspmConfig.MrcDataSaving = 0; + mupd->FspmConfig.MrcFastBoot = 1; + + mupd->FspmConfig.PrimaryVideoAdaptor = 2; +} diff --git a/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc new file mode 100644 index 0000000000..4b48156a52 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += gpio.c diff --git a/src/mainboard/kontron/mal10/variants/mal10/board_info.txt b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt new file mode 100644 index 0000000000..ce668920f5 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-mAL10 +Board URL: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/variants/mal10/data.vbt b/src/mainboard/kontron/mal10/variants/mal10/data.vbt Binary files differnew file mode 100644 index 0000000000..25be675548 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/data.vbt diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb new file mode 100644 index 0000000000..1421cb7905 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/apollolake + + register "enable_vtd" = "1" + register "dptf_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 00.1 on end # DPTF + device pci 00.2 off end # NPK + device pci 02.0 on end # iGPU + device pci 03.0 off end # Iunit + device pci 0d.0 on end # P2SB + device pci 0d.1 on end # PMC + device pci 0d.2 on end # SPI + device pci 0d.3 on end # Shared SRAM + device pci 0e.0 on end # Audio + device pci 0f.0 on end # TXE + device pci 11.0 off end # ISH + device pci 12.0 on end # SATA + device pci 13.0 on # PCIe-A 1 (Root Port 2) + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + end + device pci 13.1 on # PCIe-A 2 (Root Port 3) + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + end + device pci 13.2 on # PCIe-A 3 (Root Port 4) + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + end + device pci 13.3 on # PCIe-A 4 (Root Port 5) + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + end + device pci 14.0 on # PCIe-B 1 (Root Port 0) + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + end + device pci 14.1 off # PCIe-B 2 (Root Port 1) + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + end + device pci 15.0 on end # XHCI + device pci 15.1 off end # XDCI + device pci 16.0 off end # I2C 0 + device pci 16.1 off end # I2C 1 + device pci 16.2 off end # I2C 2 + device pci 16.3 off end # I2C 3 + device pci 17.0 off end # I2C 4 + device pci 17.1 off end # I2C 5 + device pci 17.2 off end # I2C 6 + device pci 17.3 off end # I2C 7 + device pci 18.0 off end # HSUART 0 + device pci 18.1 off end # HSUART 1 + device pci 18.2 off end # UART 2 + device pci 18.3 off end # UART 3 + device pci 19.0 off end # SPI 0 + device pci 19.1 off end # SPI 1 + device pci 19.2 off end # SPI 2 + device pci 1a.0 on end # PWM + device pci 1b.0 on end # SDCARD + device pci 1c.0 on end # eMMC + device pci 1d.0 off end # UFS + device pci 1e.0 off end # SDIO + device pci 1f.0 on # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip ec/kontron/kempld + device generic 0.0 on # UART #0 + register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" + end + device generic 0.1 on # UART #1 + register "uart[1]" = "{ KEMPLD_UART_2F8, 3 }" + end + device generic 1.0 on # I2C + register "i2c_frequency" = "KEMPLD_I2C_FREQ_FAST_MODE_400KHZ" + end + end + end # LPC + device pci 1f.1 on # SMBUS + chip drivers/i2c/nct7802y # Hardware Monitor + register "sensors" = "{ \ + .local_enable = 1, \ + .rtd[2] = RTD_VOLTAGE_MODE, \ + .rtd[1] = RTD_VOLTAGE_MODE, \ + .rtd[0] = RTD_THERMISTOR_MODE, \ + }" + # FAN0 + register "fan[0].mode" = "FAN_SMART" + register "fan[0].smart.mode" = "SMART_FAN_RPM" + register "fan[0].smart.tempsrc" = "TEMP_SOURCE_REMOTE_1" + register "fan[0].smart.table" = "{ { 49, 0 }, + { 50, 6350 }, + { 70, 9550 }, + { 90, 12750 } }" + register "fan[0].smart.critical_temp" = "95" + # FAN1 + register "fan[1].mode" = "FAN_SMART" + register "fan[1].smart.mode" = "SMART_FAN_RPM" + register "fan[1].smart.tempsrc" = "TEMP_SOURCE_LOCAL" + register "fan[1].smart.table" = "{ { 49, 0 }, + { 50, 6350 }, + { 70, 9550 }, + { 90, 12750 } }" + register "fan[1].smart.critical_temp" = "95" + device i2c 0x2e on end + end + end # SMBUS + end + chip drivers/crb + # Resource allocation reserves memory. + # This is required for correct use of TPM + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads b/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads new file mode 100644 index 0000000000..fee0ce85c0 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP1, eDP, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c new file mode 100644 index 0000000000..1e88e38e5f --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/variant/gpio.h" + +static const struct pad_config gpio_table[] = { + /* SPI */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + + /* SMBUS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + + /* LPC */ + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void variant_early_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h new file mode 100644 index 0000000000..d97e199fb8 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAL_10_CFG_GPIO_H +#define MAL_10_CFG_GPIO_H + +#include <gpio.h> +#include <stddef.h> + +void variant_early_gpio_configure(void); + +#endif /* MAL_10_CFG_GPIO_H */ |