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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-10-27 17:40:22 +0100 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-28 13:39:51 +0000 |
| commit | 19185531900aa52e7789dc2fd9c08f8d3463d189 (patch) | |
| tree | 957055354b0b08d249f679c0e9368d74eeb5fcd7 | |
| parent | 7a36ca5a3af464bab21e61256e41c4c8eb220f7d (diff) | |
| download | coreboot-19185531900aa52e7789dc2fd9c08f8d3463d189.tar.xz | |
soc/intel/xeon_sp: Lock PAM and SMRAM registers
The CedarIsland FSP Integration recommends locking down some things.
Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 592a316e06..a3076a8035 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -68,6 +68,18 @@ static void chip_final(void *data) { /* Lock SBI */ pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK); + + /* LOCK PAM */ + pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); + + /* + * LOCK SMRAM + * According to the CedarIsland FSP Integration Guide this needs to + * be done with legacy 0xCF8/0xCFC IO ops. + */ + uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); + pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); + p2sb_hide(); set_bios_init_completion(); |