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authorPhilipp Hug <philipp@hug.cx>2018-09-13 18:11:56 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-14 09:28:06 +0000
commit199b75f58a0ffc2ad0871eb4853ca425c78b4893 (patch)
treefdd1d98ffa45c1e02372f5528f414008de498911
parent31dbfbc405ba7b26cacd2cfcaeff95e52d60ad99 (diff)
downloadcoreboot-199b75f58a0ffc2ad0871eb4853ca425c78b4893.tar.xz
arch/riscv: provide a monotonic timer
The RISC-V Privileged Architecture specification defines the Machine Time Registers (mtime and mtimecmp) in section 3.1.15. Makes it possible to use the generic udelay. The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc, sifive and ucb soc. Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27434 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/arch/riscv/Kconfig4
-rw-r--r--src/arch/riscv/Makefile.inc6
-rw-r--r--src/arch/riscv/arch_timer.c28
-rw-r--r--src/arch/riscv/include/arch/io.h10
-rw-r--r--src/arch/riscv/misc.c4
-rw-r--r--src/soc/lowrisc/lowrisc/Kconfig3
-rw-r--r--src/soc/sifive/fu540/Kconfig4
-rw-r--r--src/soc/ucb/riscv/Kconfig3
8 files changed, 58 insertions, 4 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 916e269b32..2d53f422c1 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -28,3 +28,7 @@ config ARCH_ROMSTAGE_RISCV
config ARCH_RAMSTAGE_RISCV
bool
default n
+
+config RISCV_USE_ARCH_TIMER
+ bool
+ default n
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index f4b69bb95e..50c1ae69d6 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -56,6 +56,8 @@ bootblock-y += \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
+bootblock-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
+
$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
@@ -82,6 +84,8 @@ romstage-y += \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
+romstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
+
# Build the romstage
$(objcbfs)/romstage.debug: $$(romstage-objs)
@@ -118,6 +122,8 @@ ramstage-y += \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
+ramstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
+
$(eval $(call create_class_compiler,rmodules,riscv))
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c
new file mode 100644
index 0000000000..78157e6063
--- /dev/null
+++ b/src/arch/riscv/arch_timer.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Philipp Hug <philipp@hug.cx>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/encoding.h>
+#include <console/console.h>
+#include <stddef.h>
+#include <timer.h>
+#include <mcall.h>
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ if (HLS()->time == NULL)
+ die("time not set in HLS");
+ mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time)));
+}
diff --git a/src/arch/riscv/include/arch/io.h b/src/arch/riscv/include/arch/io.h
index 5f66a239b4..6fd0cac88e 100644
--- a/src/arch/riscv/include/arch/io.h
+++ b/src/arch/riscv/include/arch/io.h
@@ -33,6 +33,11 @@ static __always_inline uint32_t read32(const volatile void *addr)
return *((volatile uint32_t *)(addr));
}
+static __always_inline uint64_t read64(const volatile void *addr)
+{
+ return *((volatile uint64_t *)(addr));
+}
+
static __always_inline void write8(volatile void *addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
@@ -48,4 +53,9 @@ static __always_inline void write32(volatile void *addr, uint32_t value)
*((volatile uint32_t *)(addr)) = value;
}
+static __always_inline void write64(volatile void *addr, uint64_t value)
+{
+ *((volatile uint64_t *)(addr)) = value;
+}
+
#endif
diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c
index 65b8ecf02f..1909dbc5f1 100644
--- a/src/arch/riscv/misc.c
+++ b/src/arch/riscv/misc.c
@@ -16,7 +16,3 @@
void init_timer(void)
{
}
-
-void udelay(unsigned int n)
-{
-}
diff --git a/src/soc/lowrisc/lowrisc/Kconfig b/src/soc/lowrisc/lowrisc/Kconfig
index 71078b5c25..8b35231642 100644
--- a/src/soc/lowrisc/lowrisc/Kconfig
+++ b/src/soc/lowrisc/lowrisc/Kconfig
@@ -6,6 +6,9 @@ config SOC_LOWRISC_LOWRISC
select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
select DRIVERS_UART_8250MEM_32
+ select GENERIC_UDELAY
+ select HAVE_MONOTONIC_TIMER
+ select RISCV_USE_ARCH_TIMER
bool
default n
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index 457d16bb4e..bee8292199 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -20,7 +20,11 @@ config SOC_SIFIVE_FU540
select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
select DRIVERS_UART_SIFIVE
+ select GENERIC_UDELAY
+ select HAVE_MONOTONIC_TIMER
+ select RISCV_USE_ARCH_TIMER
select UART_OVERRIDE_REFCLK
+
if SOC_SIFIVE_FU540
config RISCV_ARCH
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index 2a73f5c284..26adb56bfe 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -5,6 +5,9 @@ config SOC_UCB_RISCV
select ARCH_ROMSTAGE_RISCV
select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
+ select GENERIC_UDELAY
+ select HAVE_MONOTONIC_TIMER
+ select RISCV_USE_ARCH_TIMER
bool
default n