diff options
| author | Jitao Shi <jitao.shi@mediatek.com> | 2019-10-21 16:47:18 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-23 13:35:26 +0000 |
| commit | 19e961e83c4200de78cbbb9e8e5800c535619a42 (patch) | |
| tree | ed7a0af172bc1da20629c5559243b8279b4daaaf | |
| parent | 68ff7298ecae29d524a6a082c6cc9057df8f5789 (diff) | |
| download | coreboot-19e961e83c4200de78cbbb9e8e5800c535619a42.tar.xz | |
soc/mediatek/mt8183: fine tune the phy timing
To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.
BUG=b:138344447
BRANCH=kukui
TEST=Boots correctly on kukui
Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
| -rw-r--r-- | src/soc/mediatek/common/dsi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 679bec8d75..2b4fac7d42 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -81,9 +81,9 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) memset(phy_timing, 0, sizeof(*phy_timing)); phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); phy_timing->ta_go = 4U * phy_timing->lpx; phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; |