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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-16 14:55:44 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:35:02 +0000 |
| commit | 1a8d0e58862517d30939d419808692250cd555ce (patch) | |
| tree | 12e7aa923b01b278f7a411e00af5d06f3a7598a2 | |
| parent | b9d95c5f643650db7b1b25fa000ccf2b25f3b634 (diff) | |
| download | coreboot-1a8d0e58862517d30939d419808692250cd555ce.tar.xz | |
soc/nvidia/tegra124/spi.c: Remove repeated word
Change-Id: I0018ea16f304a0d2cedfbd55525ecabbf2d89aa1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
| -rw-r--r-- | src/soc/nvidia/tegra124/spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 3a078f8573..4e0285de5b 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -605,7 +605,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf, * When we enable caching we'll need to clean/invalidate portions of * memory. So we need to be careful about memory alignment. Also, DMA * likes to operate on 4-bytes at a time on the AHB side. So for - * example, if we only want to receive 1 byte, 4 bytes will be be + * example, if we only want to receive 1 byte, 4 bytes will be * written in memory even if those extra 3 bytes are beyond the length * we want. * |