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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-22 14:44:58 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-23 20:08:59 +0000 |
| commit | 227c64952218c7ac02548f15bb9fe1bae9ed9e02 (patch) | |
| tree | f66f82134f87bd6d91dfcabb2b5e18aebe6691d2 | |
| parent | c3c7f8fc60eea829a8cf5e3b02cf7de9cd7c5792 (diff) | |
| download | coreboot-227c64952218c7ac02548f15bb9fe1bae9ed9e02.tar.xz | |
soc/amd/cezanne: select HAVE_EM100_SUPPORT
This makes the EM100 option visible in Kconfig that makes sure that the
SPI settings that coreboot applies are valid for the EM100 that has some
limitations on the maximum SPI frequency and possibly on the supported
SPI modes. For the PSP SPI settings, the mainboard still might need to
provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and
EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly
integrated for Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7a69cc7f5e..5e0e1a6d6d 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -22,6 +22,7 @@ config SOC_SPECIFIC_OPTIONS select FSP_COMPRESS_FSP_S_LZMA select HAVE_ACPI_TABLES select HAVE_CF9_RESET + select HAVE_EM100_SUPPORT select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE |