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authorSeunghwan Kim <sh_.kim@samsung.corp-partner.google.com>2020-04-23 14:04:38 +0900
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:10:13 +0000
commit24a65f8019e7b9b000bc8b7eb2947a07e6424293 (patch)
treeb0e0bc14ee3335f9033bd28802b30a626b74123f
parente0b7a88f586d746c72da1fedfbeda3156faf4d73 (diff)
downloadcoreboot-24a65f8019e7b9b000bc8b7eb2947a07e6424293.tar.xz
mb/google/nightfury: Tune the usb2_port[0] strength
Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/google/hatch/variants/nightfury/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
index 4b985d933e..2c759bc4bb 100644
--- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
@@ -23,7 +23,7 @@ chip soc/intel/cannonlake
# Enable DMIC1
register "PchHdaAudioLinkDmic1" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0
+ register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_EMPTY"
register "usb2_ports[3]" = "USB2_PORT_EMPTY"