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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-16 14:56:28 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:35:48 +0000 |
| commit | 26e880e8a3ed87bbc918692e929fa7e1560cb3e3 (patch) | |
| tree | 3cd0dda2037d73a67782f7ed0b374dd34c533846 | |
| parent | 9148cd145fd3a8cca04d40a05e139ad3a7251acf (diff) | |
| download | coreboot-26e880e8a3ed87bbc918692e929fa7e1560cb3e3.tar.xz | |
soc/intel/common/block/include/intelblocks/pmc_ipc.h: Remove repeated word
Change-Id: I646583f7f0d0e0f6a91bc99b7edda964337d837e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pmc_ipc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index fbf9a6ee0e..71adf5bb9b 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -58,7 +58,7 @@ enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, * Provides an ACPI method in the SSDT to read/write to the IPC mailbox which is * defined in the PMC device MMIO address space. * - * One possible use of this method is to to enable/disable the clock for a + * One possible use of this method is to enable/disable the clock for a * particular PCIe root port at runtime when the device is in D3 state. * * The ACPI method takes 7 arguments: |