diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2018-03-19 17:15:20 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-04-05 15:59:28 +0000 |
| commit | 2a50a1f534177965651244557198ee05235f8891 (patch) | |
| tree | 8b20a4e2d7805a30e07db9badd6ae4bc844724e1 | |
| parent | 8e50b6d63dd05bbc23e2d55a35df77ddb1ba4575 (diff) | |
| download | coreboot-2a50a1f534177965651244557198ee05235f8891.tar.xz | |
soc/intel/cannonlake: Clear EMMC timeout when boot source is not EMMC
Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide. _PS0 is not called by kernel when boot source is not
EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to
cover cases that the system doesn't boot from EMMC.
BUG=b:76202699
TEST=Install OS into EMMC
Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/scs.asl | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 4062e704a1..896fd77c19 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -16,6 +16,17 @@ #include <soc/pcr_ids.h> Scope (\_SB.PCI0) { + + /* + * Clear register 0x1C20/0x4820 + * Arg0 - PCR Port ID + */ + Method(SCSC, 1, Serialized) + { + ^PCRA (Arg0, 0x1C20, 0x0) + ^PCRA (Arg0, 0x4820, 0x0) + } + /* EMMC */ Device(PEMC) { Name(_ADR, 0x001A0000) @@ -31,14 +42,18 @@ Scope (\_SB.PCI0) { PGEN, 1, /* PG_ENABLE */ } + Method(_INI) { + /* Clear register 0x1C20/0x4820 */ + ^^SCSC (PID_EMMC) + } + Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us Store(0, PGEN) // Disable PG /* Clear register 0x1C20/0x4820 */ - ^^PCRA (PID_EMMC, 0x1C20, 0x0) - ^^PCRA (PID_EMMC, 0x4820, 0x0) + ^^SCSC (PID_EMMC) /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) @@ -80,13 +95,18 @@ Scope (\_SB.PCI0) { PGEN, 1, /* PG_ENABLE */ } + Method(_INI) + { + /* Clear register 0x1C20/0x4820 */ + ^^SCSC (PID_SDX) + } + Method (_PS0, 0, Serialized) { Store (0, PGEN) /* Disable PG */ /* Clear register 0x1C20/0x4820 */ - ^^PCRA (PID_SDX, 0x1C20, 0x0) - ^^PCRA (PID_SDX, 0x4820, 0x0) + ^^SCSC (PID_SDX) /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) |