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| author | John Zhao <john.zhao@intel.com> | 2021-02-16 09:22:47 -0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-23 22:14:04 +0000 |
| commit | 2c7842407af8e84b28d41e8369ccf199748f65ce (patch) | |
| tree | 304d4206cb923aba3e058bc32bf30e75e8676876 | |
| parent | 83e6c15b0ea252d5475c3a5af25279765e19aa4d (diff) | |
| download | coreboot-2c7842407af8e84b28d41e8369ccf199748f65ce.tar.xz | |
soc/intel/tigerlake: Remove polling for Link Active Status at resume
Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not
applicable for SW CM platform at the resume sequence. This change
removes the pollng for "LA == 1" to improve resume performance.
BUG=b:177519081
TEST=Boot to kernel and validated s0ix on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 39180f7393..0453f1c7d4 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -144,18 +144,6 @@ Method (D3CX, 0, Serialized) Local1 = L23R } STAT = 0x1 - - /* Wait for LA = 1 */ - Local0 = 0 - Local1 = LASX - While (Local1 == 0) { - If (Local0 > 20) { - Break - } - Sleep(5) - Local0++ - Local1 = LASX - } } /* |