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| author | Angel Pons <th3fanbus@gmail.com> | 2019-12-31 14:26:23 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-01 16:10:36 +0000 |
| commit | 3473f76e903611a947eb03f8ae89e360947b1ae4 (patch) | |
| tree | 6e0ce29e1d61b6df6220fbee606f5add0276b2fc | |
| parent | 2a9a49b7ba0d43eaa54af089966bf6859d05ac28 (diff) | |
| download | coreboot-3473f76e903611a947eb03f8ae89e360947b1ae4.tar.xz | |
nb/intel/sandybridge: Use the MC_BIOS_DATA define
Change-Id: I177f419d2675ebda5c231a257bed8baf56e13291
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index cab5588ced..aa166c9d73 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -154,7 +154,7 @@ static void report_memory_config(void) addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50)/100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, |