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authorAngel Pons <th3fanbus@gmail.com>2021-05-17 15:54:32 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-05-20 17:47:20 +0000
commit348639c4603852f70c161aa58b986e1a7e37962e (patch)
treeb3612651cad4646ac301121457e370273ba90792
parent13d5d98bd580c1f67579c59807f8d14a733086f3 (diff)
downloadcoreboot-348639c4603852f70c161aa58b986e1a7e37962e.tar.xz
mb/asus/p8h61-m_lx3_r2_0: List all PCH PCIe RPs in devicetree
Done to preserve reproducibility when switching to overridetrees. The H61 PCH only supports 6 PCIe root ports anyway. Change-Id: I926d62dda512e435d44c0646083c7722427dc80b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54386 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
index 62dbb378c2..1ae77ad2b0 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
@@ -37,6 +37,8 @@ chip northbridge/intel/sandybridge
device pci 1c.3 on end # RP #4: PCIEX1_1
device pci 1c.4 on end # RP #5: PCIEX1_2
device pci 1c.5 on end # RP #6: RTL8111 GbE NIC
+ device pci 1c.6 off end # RP #7
+ device pci 1c.7 off end # RP #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge