soc/amd/common: Drop ACPIMMIO GPIO bank separation

The banks are one after each other in the ACPIMMIO space. Also
there is space for more banks and existing ASL takes advantage
of the property.

Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 74 insertions, 101 deletions

diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index d67e2d05f9..9125308307 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -82,79 +82,60 @@ static void get_sci_config_bits(uint32_t flag, uint32_t *edge, uint32_t *level)
 
 uintptr_t gpio_get_address(gpio_t gpio_num)
 {
-	uintptr_t gpio_address;
+	return (uintptr_t)gpio_ctrl_ptr(gpio_num);
+}
+
+static void __gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or)
+{
+	uint32_t reg;
+
+	reg = gpio_read32(gpio_num);
+	reg &= mask;
+	reg |= or;
+	gpio_write32(gpio_num, reg);
+}
 
-	if (gpio_num < 64)
-		gpio_address = GPIO_BANK0_CONTROL(gpio_num);
-	else if (gpio_num < 128)
-		gpio_address = GPIO_BANK1_CONTROL(gpio_num);
-	else
-		gpio_address = GPIO_BANK2_CONTROL(gpio_num);
+static void __gpio_and32(gpio_t gpio_num, uint32_t mask)
+{
+	__gpio_update32(gpio_num, mask, 0);
+}
 
-	return gpio_address;
+static void __gpio_or32(gpio_t gpio_num, uint32_t or)
+{
+	__gpio_update32(gpio_num, -1UL, or);
 }
 
 int gpio_get(gpio_t gpio_num)
 {
 	uint32_t reg;
-	uintptr_t gpio_address = gpio_get_address(gpio_num);
-
-	reg = read32((void *)gpio_address);
 
+	reg = gpio_read32(gpio_num);
 	return !!(reg & GPIO_PIN_STS);
 }
 
 void gpio_set(gpio_t gpio_num, int value)
 {
-	uint32_t reg;
-	uintptr_t gpio_address = gpio_get_address(gpio_num);
-
-	reg = read32((void *)gpio_address);
-	reg &= ~GPIO_OUTPUT_MASK;
-	reg |=  !!value << GPIO_OUTPUT_SHIFT;
-	write32((void *)gpio_address, reg);
+	__gpio_update32(gpio_num, ~GPIO_OUTPUT_MASK, !!value << GPIO_OUTPUT_SHIFT);
 }
 
 void gpio_input_pulldown(gpio_t gpio_num)
 {
-	uint32_t reg;
-	uintptr_t gpio_address = gpio_get_address(gpio_num);
-
-	reg = read32((void *)gpio_address);
-	reg &= ~GPIO_PULLUP_ENABLE;
-	reg |=  GPIO_PULLDOWN_ENABLE;
-	write32((void *)gpio_address, reg);
+	__gpio_update32(gpio_num, ~GPIO_PULLUP_ENABLE, GPIO_PULLDOWN_ENABLE);
 }
 
 void gpio_input_pullup(gpio_t gpio_num)
 {
-	uint32_t reg;
-	uintptr_t gpio_address = gpio_get_address(gpio_num);
-
-	reg = read32((void *)gpio_address);
-	reg &= ~GPIO_PULLDOWN_ENABLE;
-	reg |=  GPIO_PULLUP_ENABLE;
-	write32((void *)gpio_address, reg);
+	__gpio_update32(gpio_num, ~GPIO_PULLDOWN_ENABLE, GPIO_PULLUP_ENABLE);
 }
 
 void gpio_input(gpio_t gpio_num)
 {
-	uint32_t reg;
-	uintptr_t gpio_address = gpio_get_address(gpio_num);
-
-	reg = read32((void *)gpio_address);
-	reg &= ~GPIO_OUTPUT_ENABLE;
-	write32((void *)gpio_address, reg);
+	__gpio_and32(gpio_num, ~GPIO_OUTPUT_ENABLE);
 }
 
 void gpio_output(gpio_t gpio_num, int value)
 {
-	uint32_t reg;
-	uintptr_t gpio_address = gpio_get_address(gpio_num);
-
-	reg = read32((void *)gpio_address);
-	reg |=  GPIO_OUTPUT_ENABLE;
-	write32((void *)gpio_address, reg);
+	__gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE);
 	gpio_set(gpio_num, value);
 }
 
@@ -210,7 +191,7 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 
 		soc_gpio_hook(gpio, mux);
 
-		gpio_ptr = (uint32_t *)gpio_get_address(gpio);
+		gpio_ptr = gpio_ctrl_ptr(gpio);
 
 		if (control_flags & GPIO_SPECIAL_FLAG) {
 			gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items);
@@ -276,13 +257,12 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 
 int gpio_interrupt_status(gpio_t gpio)
 {
-	uintptr_t gpio_address = gpio_get_address(gpio);
-	uint32_t reg = read32((void *)gpio_address);
+	uint32_t reg = gpio_read32(gpio);
 
 	if (reg & GPIO_INT_STATUS) {
 		/* Clear interrupt status, preserve wake status */
 		reg &= ~GPIO_WAKE_STATUS;
-		write32((void *)gpio_address, reg);
+		gpio_write32(gpio, reg);
 		return 1;
 	}
 
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index d3deff1153..2775b52116 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -353,6 +353,28 @@ static inline void gpio_100_write32(uint8_t reg, uint32_t value)
 }
 
 /* New GPIO banks configuration registers */
+
+static inline void *gpio_ctrl_ptr(uint8_t gpio_num)
+{
+	return acpimmio_gpio0 + gpio_num * sizeof(uint32_t);
+}
+
+static inline uint32_t gpio_read32(uint8_t gpio_num)
+{
+	return read32(gpio_ctrl_ptr(gpio_num));
+}
+
+static inline void gpio_write32(uint8_t gpio_num, uint32_t value)
+{
+	write32(gpio_ctrl_ptr(gpio_num), value);
+}
+
+static inline void gpio_write32_rb(uint8_t gpio_num, uint32_t value)
+{
+	write32(gpio_ctrl_ptr(gpio_num), value);
+	read32(gpio_ctrl_ptr(gpio_num));
+}
+
 /* GPIO bank 0 */
 static inline uint8_t gpio0_read8(uint8_t reg)
 {
diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h
index f4288aa072..da65e08d70 100644
--- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h
+++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h
@@ -5,7 +5,6 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <amdblocks/acpimmio.h>
 
 struct soc_amd_gpio {
 	uint8_t gpio;
@@ -19,10 +18,6 @@ struct soc_amd_event {
 	uint8_t event;
 };
 
-#define GPIO_BANK0_CONTROL(gpio) ((uintptr_t)acpimmio_gpio0 + ((gpio) * 4))
-#define GPIO_BANK1_CONTROL(gpio) ((uintptr_t)acpimmio_gpio1 + (((gpio) - 64) * 4))
-#define GPIO_BANK2_CONTROL(gpio) ((uintptr_t)acpimmio_gpio2 + (((gpio) - 128) * 4))
-
 #define GPIO_MASTER_SWITCH	0xFC
 #define   GPIO_MASK_STS_EN	BIT(28)
 #define   GPIO_INTERRUPT_EN	BIT(30)
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index c868c3458a..75509eb4c1 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -302,7 +302,7 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
 					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 		return -1;
 	}
-	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+	uintptr_t addr = gpio_get_address(gpio_num);
 
 	acpigen_soc_get_gpio_in_local5(addr);
 
@@ -332,7 +332,7 @@ static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
 					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 		return -1;
 	}
-	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+	uintptr_t addr = gpio_get_address(gpio_num);
 
 	/* Store (0x40, Local0) */
 	acpigen_write_store();
diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c
index 6f34573aa9..881278f254 100644
--- a/src/soc/amd/picasso/i2c.c
+++ b/src/soc/amd/picasso/i2c.c
@@ -154,23 +154,16 @@ static const struct soc_amd_gpio i2c_2_gpi[] = {
 static void save_i2c_pin_registers(uint8_t gpio,
 					struct soc_amd_i2c_save *save_table)
 {
-	uint32_t *gpio_ptr;
-
-	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
 	save_table->mux_value = iomux_read8(gpio);
-	save_table->control_value = read32(gpio_ptr);
+	save_table->control_value = gpio_read32(gpio);
 }
 
 static void restore_i2c_pin_registers(uint8_t gpio,
 					struct soc_amd_i2c_save *save_table)
 {
-	uint32_t *gpio_ptr;
-
-	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
 	iomux_write8(gpio, save_table->mux_value);
 	iomux_read8(gpio);
-	write32(gpio_ptr, save_table->control_value);
-	read32(gpio_ptr);
+	gpio_write32_rb(gpio, save_table->control_value);
 }
 
 /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
@@ -196,19 +189,19 @@ void sb_reset_i2c_slaves(void)
 	 */
 	for (j = 0; j < 9; j++) {
 		if (control & GPIO_I2C2_SCL)
-			write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW);
+			gpio_write32(I2C2_SCL_PIN, GPIO_OUTPUT_ENABLE);
 		if (control & GPIO_I2C3_SCL)
-			write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW);
+			gpio_write32(I2C3_SCL_PIN, GPIO_OUTPUT_ENABLE);
 
-		read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+		gpio_read32(0); /* Flush posted write */
 		udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
 
 		if (control & GPIO_I2C2_SCL)
-			write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH);
+			gpio_write32(I2C2_SCL_PIN, 0);
 		if (control & GPIO_I2C3_SCL)
-			write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH);
+			gpio_write32(I2C3_SCL_PIN, 0);
 
-		read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+		gpio_read32(0); /* Flush posted write */
 		udelay(4);
 	}
 
diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h
index 58c27a424d..34c19aaf29 100644
--- a/src/soc/amd/picasso/include/soc/i2c.h
+++ b/src/soc/amd/picasso/include/soc/i2c.h
@@ -17,11 +17,6 @@ struct soc_amd_i2c_save {
 #define I2C2_SCL_PIN			GPIO_113
 #define I2C3_SCL_PIN			GPIO_19
 
-#define GPIO_I2C2_ADDRESS		GPIO_BANK1_CONTROL(I2C2_SCL_PIN)
-#define GPIO_I2C3_ADDRESS		GPIO_BANK0_CONTROL(I2C3_SCL_PIN)
-#define GPIO_SCL_HIGH			0
-#define GPIO_SCL_LOW			GPIO_OUTPUT_ENABLE
-
 #define I2C2_SCL_PIN_IOMUX_GPIOxx	GPIO_113_IOMUX_GPIOxx
 #define I2C3_SCL_PIN_IOMUX_GPIOxx	GPIO_19_IOMUX_GPIOxx
 
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index ffead50435..19dee79a96 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -277,7 +277,7 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
 					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 		return -1;
 	}
-	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+	uintptr_t addr = gpio_get_address(gpio_num);
 
 	acpigen_soc_get_gpio_in_local5(addr);
 
@@ -307,7 +307,7 @@ static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
 					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 		return -1;
 	}
-	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+	uintptr_t addr = gpio_get_address(gpio_num);
 
 	/* Store (0x40, Local0) */
 	acpigen_write_store();
diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
index 8667d9260b..0327028241 100644
--- a/src/soc/amd/stoneyridge/i2c.c
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -137,23 +137,16 @@ static const struct soc_amd_gpio i2c_2_gpi[] = {
 static void save_i2c_pin_registers(uint8_t gpio,
 					struct soc_amd_i2c_save *save_table)
 {
-	uint32_t *gpio_ptr;
-
-	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
 	save_table->mux_value = iomux_read8(gpio);
-	save_table->control_value = read32(gpio_ptr);
+	save_table->control_value = gpio_read32(gpio);
 }
 
 static void restore_i2c_pin_registers(uint8_t gpio,
 					struct soc_amd_i2c_save *save_table)
 {
-	uint32_t *gpio_ptr;
-
-	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
 	iomux_write8(gpio, save_table->mux_value);
 	iomux_read8(gpio);
-	write32(gpio_ptr, save_table->control_value);
-	read32(gpio_ptr);
+	gpio_write32_rb(gpio, save_table->control_value);
 }
 
 /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
@@ -182,27 +175,27 @@ void sb_reset_i2c_slaves(void)
 	 */
 	for (j = 0; j < 9; j++) {
 		if (control & GPIO_I2C0_SCL)
-			write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW);
+			gpio_write32(I2C0_SCL_PIN, GPIO_OUTPUT_ENABLE);
 		if (control & GPIO_I2C1_SCL)
-			write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW);
+			gpio_write32(I2C1_SCL_PIN, GPIO_OUTPUT_ENABLE);
 		if (control & GPIO_I2C2_SCL)
-			write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW);
+			gpio_write32(I2C2_SCL_PIN, GPIO_OUTPUT_ENABLE);
 		if (control & GPIO_I2C3_SCL)
-			write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW);
+			gpio_write32(I2C3_SCL_PIN, GPIO_OUTPUT_ENABLE);
 
-		read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+		gpio_read32(0); /* Flush posted write */
 		udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
 
 		if (control & GPIO_I2C0_SCL)
-			write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH);
+			gpio_write32(I2C0_SCL_PIN, 0);
 		if (control & GPIO_I2C1_SCL)
-			write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH);
+			gpio_write32(I2C1_SCL_PIN, 0);
 		if (control & GPIO_I2C2_SCL)
-			write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH);
+			gpio_write32(I2C2_SCL_PIN, 0);
 		if (control & GPIO_I2C3_SCL)
-			write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH);
+			gpio_write32(I2C3_SCL_PIN, 0);
 
-		read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+		gpio_read32(0); /* Flush posted write */
 		udelay(4);
 	}
 
diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h
index 874f7d1565..844ff1bf2d 100644
--- a/src/soc/amd/stoneyridge/include/soc/i2c.h
+++ b/src/soc/amd/stoneyridge/include/soc/i2c.h
@@ -21,11 +21,6 @@ struct soc_amd_i2c_save {
 #define I2C2_SCL_PIN			GPIO_113
 #define I2C3_SCL_PIN			GPIO_19
 
-#define GPIO_I2C0_ADDRESS		GPIO_BANK2_CONTROL(I2C0_SCL_PIN)
-#define GPIO_I2C1_ADDRESS		GPIO_BANK2_CONTROL(I2C1_SCL_PIN)
-#define GPIO_I2C2_ADDRESS		GPIO_BANK1_CONTROL(I2C2_SCL_PIN)
-#define GPIO_I2C3_ADDRESS		GPIO_BANK0_CONTROL(I2C3_SCL_PIN)
-
 #define I2C0_SCL_PIN_IOMUX_GPIOxx	GPIO_145_IOMUX_GPIOxx
 #define I2C1_SCL_PIN_IOMUX_GPIOxx	GPIO_147_IOMUX_GPIOxx
 #define I2C2_SCL_PIN_IOMUX_GPIOxx	GPIO_113_IOMUX_GPIOxx