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authorMartin Roth <martinroth@google.com>2018-12-17 13:33:10 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-12-19 05:49:28 +0000
commit3f6891108b053f917b18b3fabebaa85c93249c27 (patch)
tree6bc0a0eff8730da25f339999ab284c749d44d011
parent286c6dfd1b81cf11a49b84e8f210b91402d8cad5 (diff)
downloadcoreboot-3f6891108b053f917b18b3fabebaa85c93249c27.tar.xz
mb/google/kahlee: Remove board_id check for Liara 2T timings
Use 2T memory timings on Liara for all board IDs. BUG=b:116082728 TEST=Build & boot on Liara Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
-rw-r--r--src/mainboard/google/kahlee/OemCustomize.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index fc8ff32901..ce70b8d6e3 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -38,7 +38,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END
};
-/* TODO: Remove when no longer needed */
+/* Liara-specific 2T memory configuration */
static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
@@ -58,7 +58,7 @@ static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 5))
+ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA))
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
else