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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-04-19 00:36:39 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-19 00:36:39 +0000
commit432461ec7fad51190cda33716b90f693de2a6ec6 (patch)
tree591a75d6961623c8e4797d306b0eef405a7155b5
parentb3ae1867d1a4b495a56078f521bebec9981f7494 (diff)
downloadcoreboot-432461ec7fad51190cda33716b90f693de2a6ec6.tar.xz
cleanup wrong use of defined() after exporting all variables in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/northbridge/amd/amdk8/incoherent_ht.c6
-rw-r--r--src/northbridge/amd/amdk8/raminit.c10
2 files changed, 6 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 534951aa6e..4b5209267d 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -7,10 +7,6 @@
#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
-#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
- #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
-#endif
-
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
#define K8_ALLOCATE_MMIO_RANGE 0
@@ -568,7 +564,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
return reset_needed;
}
-#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) // || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55)
+#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
{
uint32_t dword;
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index c4dc3f408e..2b76cffd19 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1165,7 +1165,7 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
if (unbuffered) {
if ((has_dualch) && (!is_cpu_pre_d0())) {
dcl |= DCL_UnBuffDimm;
-#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939
+#if CONFIG_CPU_AMD_SOCKET_939
if ((cpuid_eax(1) & 0x30) == 0x30) {
/* CS[7:4] is copy of CS[3:0], should be set for 939 socket */
dcl |= DCL_UpperCSMap;
@@ -1389,7 +1389,7 @@ static const unsigned char min_cycle_times[] = {
[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
};
-#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939
+#if CONFIG_CPU_AMD_SOCKET_939
/* return the minimum cycle time and set 2T accordingly */
static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) {
@@ -1511,14 +1511,14 @@ hw_error:
return dloading_cycle_time;
}
-#endif /* #if defined(CONFIG_CPU_AMD_SOCKET_939) */
+#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */
static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask)
{
/* Compute the minimum cycle time for these dimms */
struct spd_set_memclk_result result;
unsigned min_cycle_time, min_latency, bios_cycle_time;
-#if defined(CONFIG_CPU_AMD_SOCKET_939)
+#if CONFIG_CPU_AMD_SOCKET_939
unsigned dloading_cycle_time;
#endif
int i;
@@ -1674,7 +1674,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
#endif
#endif
-#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939
+#if CONFIG_CPU_AMD_SOCKET_939
dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask);
if (dloading_cycle_time > min_cycle_time) {
min_cycle_time = dloading_cycle_time;