diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-04-06 14:29:37 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-18 20:34:24 +0000 |
| commit | 4681b2778b32b8a1d1b1269e58ee4b8dd5f04f6e (patch) | |
| tree | 76efb43e0529460da8e769db9e4120a1702bb231 | |
| parent | 836ea7585658cb5a92fee3fa76ffa8bf2fde4a0d (diff) | |
| download | coreboot-4681b2778b32b8a1d1b1269e58ee4b8dd5f04f6e.tar.xz | |
soc/intel/xeon_sp: Set SATA REGLOCKs
Set the SATA and SSATA REGLOCK as indicated by the Intel documentation.
Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/lockdown.c | 17 |
2 files changed, 24 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h index 41ec7e1450..de7a73a472 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h +++ b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h @@ -13,6 +13,10 @@ /* PCH Device info */ +#define PCH_DEV_SLOT_MROM0 0x11 +#define PCH_DEVFN_SSATA _PCH_DEVFN(MROM0, 5) +#define PCH_DEV_SSATA _PCH_DEV(MROM0, 5) + #define XHCI_BUS_NUMBER 0x0 #define PCH_DEV_SLOT_XHCI 0x14 #define XHCI_FUNC_NUM 0x0 @@ -32,6 +36,12 @@ #define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) #define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) +#define SATAGC 0x9c +#define SATAGC_REGLOCK BIT(31) + #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 3a12110bef..0f032fc755 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> +#include <device/pci.h> #include <intelblocks/cfg.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> +#include <soc/pci_devs.h> #include <soc/pm.h> static void lpc_lockdown_config(int chipset_lockdown) @@ -29,13 +31,22 @@ static void pmc_lockdown_config(int chipset_lockdown) /* Make sure payload/OS can't trigger global reset */ pmc_global_reset_disable_and_lock(); + + /* Lock PMC stretch policy */ + pci_or_config32(PCH_DEV_PMC, GEN_PMCON_B, SLP_STR_POL_LOCK); +} + +static void sata_lockdown_config(int chipset_lockdown) +{ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + pci_or_config32(PCH_DEV_SATA, SATAGC, SATAGC_REGLOCK); + pci_or_config32(PCH_DEV_SSATA, SATAGC, SATAGC_REGLOCK); + } } void soc_lockdown_config(int chipset_lockdown) { - /* LPC lock down configuration */ lpc_lockdown_config(chipset_lockdown); - - /* PMC lock down configuration */ pmc_lockdown_config(chipset_lockdown); + sata_lockdown_config(chipset_lockdown); } |