diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-05-20 13:09:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-28 09:45:27 +0000 |
| commit | 4cabf789fd7615318cd0552e490c252ba0f142a6 (patch) | |
| tree | 93bbe9439b96e557e5f490fcf5b67b73b056e5c9 | |
| parent | c3568612391a5079f87acc0ea069a263e08be069 (diff) | |
| download | coreboot-4cabf789fd7615318cd0552e490c252ba0f142a6.tar.xz | |
soc/intel/tigerlake: Configure THC
Enable/Disable THCx though devicetree
BUG=None
BRANCH=None
TEST=Boot and check FSP log for THC setting
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: If7683969161be67f68f441c28c80503de39079b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 611a61035d..bdcd357173 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -17,6 +17,11 @@ #include <soc/soc_chip.h> #include <string.h> +/* THC assignment definition */ +#define THC_NONE 0 +#define THC_0 1 +#define THC_1 2 + /* * Chip config parameter PcieRpL1Substates uses (UPD value + 1) * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. @@ -221,6 +226,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->VmdEnable = 0; + /* THC */ + dev = pcidev_path_on_root(PCH_DEVFN_THC0); + if (!dev) + params->ThcPort0Assignment = 0; + else + params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE; + + dev = pcidev_path_on_root(PCH_DEVFN_THC1); + if (!dev) + params->ThcPort1Assignment = 0; + else + params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; |