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authorAngel Pons <th3fanbus@gmail.com>2021-02-08 00:24:32 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-11 10:19:31 +0000
commit4dc85f11d1001cb58ef8b00c3172a6b52783435f (patch)
tree99a439fa3113477b481cbd732044b09bd4b9fdfa
parent6f4dc8f7a4dcad373c8a5097ab43738b634cb34b (diff)
downloadcoreboot-4dc85f11d1001cb58ef8b00c3172a6b52783435f.tar.xz
sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__
Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/southbridge/intel/common/rtc.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c
index 63fc124ed2..ef30d9a53a 100644
--- a/src/southbridge/intel/common/rtc.c
+++ b/src/southbridge/intel/common/rtc.c
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#define __SIMPLE_DEVICE__
+
#include <console/console.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
@@ -9,17 +11,11 @@
#include "pmutil.h"
#include "rtc.h"
-/* PCI Configuration Space (D31:F0): LPC */
-#if defined(__SIMPLE_DEVICE__)
#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
-#else
-#define PCH_LPC_DEV pcidev_on_root(0x1f, 0)
-#endif
int rtc_failure(void)
{
- return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3)
- & RTC_BATTERY_DEAD);
+ return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) & RTC_BATTERY_DEAD);
}
void sb_rtc_init(void)