diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-03-05 17:11:14 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:26:20 +0200 |
| commit | 51ad6ac695c5353d66210b9ed77e420eb9a520ef (patch) | |
| tree | 731450bd35bde74eeb6341343be386732711f8a3 | |
| parent | 59074ff89fee709a3822d50a400834b70dd87b23 (diff) | |
| download | coreboot-51ad6ac695c5353d66210b9ed77e420eb9a520ef.tar.xz | |
pistachio: Decrease DDR ODT from 75R to 50R
The DDR On Die Termination was incorrectly configured at 75R,
where as the data sheet suggests for DDR2-800 it should be
set to 50R.
Correct this by adjusting the ODT setting in the EMR register.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
BRANCH=none
Change-Id: I2f0242c422b1cb3d1f64ce3dd17b62fef5e7e155
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac081ac59c0dc3d16a7b540cd379fb870b6cfe40
Original-Change-Id: If7951812033c4e88f4be3c143fb49526eddba142
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256304
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9846
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/imgtec/pistachio/ddr2_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index e236c1c5e5..0943cfa74c 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -240,7 +240,7 @@ int init_ddr2(void) * 15:13 RSVD * 31:16 Reserved */ - write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004); + write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044); /* MR2 : EMR2 Register * Generate to use with PHY and PCTL * 2:0 PASR, NA 000 |