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authorPatrick Rudolph <siro@das-labor.org>2016-06-14 18:48:17 +0200
committerMartin Roth <martinroth@google.com>2016-06-20 21:46:58 +0200
commit577aad6f132da51640b6fe5c72fa8f14718c5c34 (patch)
tree3f65d42e67a2aa396e4639e1fc4a0906c2bcd6e3
parentb7b1b2884fb901ac61b7fde6729f811b2e56dd3e (diff)
downloadcoreboot-577aad6f132da51640b6fe5c72fa8f14718c5c34.tar.xz
include/device/dram/ddr3: Add additional frequencies
IvyBridge memory controller supports more frequencies than SandyBridge. Required for future patches. Change-Id: I0bcb670c20407ec0aec20bae85c4cbe6ccc44b16 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15182 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/include/device/dram/ddr3.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index d58cdce8e1..eae7840fd2 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -35,9 +35,13 @@
*/
#define TCK_1333MHZ 192
#define TCK_1200MHZ 212
+#define TCK_1100MHZ 232
#define TCK_1066MHZ 240
+#define TCK_1000MHZ 256
#define TCK_933MHZ 274
+#define TCK_900MHZ 284
#define TCK_800MHZ 320
+#define TCK_700MHZ 365
#define TCK_666MHZ 384
#define TCK_533MHZ 480
#define TCK_400MHZ 640