diff options
author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-04 15:14:29 +0100 |
---|---|---|
committer | Patrick Rudolph <siro@das-labor.org> | 2019-03-16 09:01:50 +0000 |
commit | 5926ae24a6fa4ebf83f24281c3df88b61076b838 (patch) | |
tree | bb64e20821959f34603fd5bd72502d6da4dd18dd | |
parent | 0e3f7d47804d39912faec5a56bc9cddf91ea354b (diff) | |
download | coreboot-5926ae24a6fa4ebf83f24281c3df88b61076b838.tar.xz |
drivers/intel/fsp1_0: Deduplicate code
Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0.
Allows to have a common entry after FSP-M.
Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
-rw-r--r-- | src/drivers/intel/fsp1_0/fsp_util.c | 12 | ||||
-rw-r--r-- | src/drivers/intel/fsp1_0/fsp_util.h | 4 | ||||
-rw-r--r-- | src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 13 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 12 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/romstage.h | 1 | ||||
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 13 | ||||
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/include/soc/romstage.h | 2 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.h | 2 |
8 files changed, 15 insertions, 44 deletions
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 2da07d519b..4e50abae4e 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -23,6 +23,7 @@ #include <ip_checksum.h> #include <timestamp.h> #include <cpu/intel/microcode.h> +#include <cf9_reset.h> #ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ @@ -63,6 +64,17 @@ void FspNotify (u32 Phase) #ifdef __PRE_RAM__ +/* The FSP returns here after the fsp_early_init call */ +static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) +{ + *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; + + if (Status == 0xFFFFFFFF) + system_reset(); + + romstage_main_continue(Status, HobListPtr); +} + /* * Call the FSP to do memory init. The FSP doesn't return to this function. * The FSP returns to the romstage_main_continue(). diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index f781329d21..e0da19e8ac 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -32,10 +32,12 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer); void print_fsp_info(void); void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); -void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); void *find_saved_temp_mem(void *hob_list_ptr); void *find_fsp_reserved_mem(void *hob_list_ptr); +/* function in romstage.c */ +void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); + /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ec36c06c16..04a696c2c2 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <bootstate.h> #include <cbmem.h> -#include <cf9_reset.h> #include <device/device.h> #include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp1_0/fsp_util.h> @@ -166,16 +165,4 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, - VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; - - if (Status == 0xFFFFFFFF) { - system_reset(); - } - romstage_main_continue(Status, HobListPtr); -} - #endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c9cbcfe960..7e90142250 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -336,16 +336,4 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, - VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; - - if (Status == 0xFFFFFFFF) { - system_reset(); - } - romstage_main_continue(Status, HobListPtr); -} - #endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 9cbc95c240..5f0bd8d9c3 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -27,7 +27,6 @@ void report_platform_info(void); #include <drivers/intel/fsp1_0/fsp_util.h> void main(FSP_INFO_HEADER *fsp_info_header); -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 54e796d48d..fd8ca38ab6 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -20,7 +20,6 @@ #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> -#include <cf9_reset.h> #include <device/device.h> #include <device/pci_def.h> #include <drivers/intel/fsp1_0/fsp_util.h> @@ -140,15 +139,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fs return; } - -/* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) -{ - *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; - - if (Status == 0xFFFFFFFF) { - system_reset(); - } - - romstage_main_continue(Status, HobListPtr); -} diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h index 877b0a0b70..63b7fbaff9 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h @@ -24,8 +24,6 @@ #include <stdint.h> #include <fsp.h> -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); - #define NUM_ROMSTAGE_TS 4 void early_mainboard_romstage_entry(void); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 261357746f..5827b0fe9b 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -29,6 +29,4 @@ void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask); -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); - #endif /* _RANGELEY_ROMSTAGE_H_ */ |