diff options
author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-09 21:53:58 +0200 |
---|---|---|
committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-17 21:53:38 +0000 |
commit | 5d1a328e88674e64878954674f45f0a09120fc98 (patch) | |
tree | c918065cb03a7f051bb9875f67781045ac43b5c6 | |
parent | b349f258a99d4e56e875b7dbf86fa2368d196a41 (diff) | |
download | coreboot-5d1a328e88674e64878954674f45f0a09120fc98.tar.xz |
soc/intel/cannonlake: add missing special function pads
The following parameters do nothing else than configuring the
corresponding pads to native mode:
- DdiPortEdp
- DdiPort*Hpd
- DdiPort*Ddc
- GpioDdp*
- SpiGpioAssign
- I2c*GpioAssign
- SerialIoUartDebugEnable
- Gp*GpioAssign
- Uart*GpioAssign
- GpioEnableHdaLink
- AudioLinkDmic*
- AudioLinkSsp*
- GpioEnableHdaSspMasterClock
- AudioLinkSndw*
- SmbAlertEnable
Add the missing special function gpio pad groups for CNL, to be able to
configure them via gpio.h instead having to set various FSP parameters.
The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.
Also, see soc/intel/tigerlake for reference.
Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
-rw-r--r-- | src/soc/intel/cannonlake/acpi/gpio.asl | 2 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/gpio.c | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/gpio_cnp_h.c | 4 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h | 50 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h | 8 |
5 files changed, 38 insertions, 30 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 71524decba..2a4534330f 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -73,7 +73,7 @@ Method (GADD, 1, NotSerialized) Subtract (Arg0, GPP_D0, Local1) } /* GPIO Community 2 */ - If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) + If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, DRAM_RESET_B))) { Store (PID_GPIOCOM2, Local0) Subtract (Arg0, GPD0, Local1) diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 8e08a4b80b..3c70ad9a5b 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -47,7 +47,7 @@ static const struct pad_group cnl_community1_groups[] = { /* This community is not visible to the OS */ static const struct pad_group cnl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ + INTEL_GPP(GPD0, GPD0, DRAM_RESET_B), /* GPD */ }; /* This community is not visible to the OS */ @@ -108,7 +108,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, - .last_pad = GPD11, + .last_pad = DRAM_RESET_B, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index a7b1781e82..06e344d16f 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -47,7 +47,7 @@ static const struct pad_group cnl_community1_groups[] = { /* This community is not visible to the OS */ static const struct pad_group cnl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ + INTEL_GPP(GPD0, GPD0, DRAM_RESET_B), /* GPD */ }; static const struct pad_group cnl_community3_groups[] = { @@ -110,7 +110,7 @@ static const struct pad_community cnl_communities[] = { [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, - .last_pad = GPD11, + .last_pad = DRAM_RESET_B, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index b5d34dcb5f..48cbacb8e1 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -183,7 +183,7 @@ #define GPP_H21 138 #define GPP_H22 139 #define GPP_H23 140 -/* Group VGPIO */ +/* Group VGPIO 0 */ #define CNV_BTEN 141 #define CNV_GNEN 142 #define CNV_WFEN 143 @@ -216,6 +216,7 @@ #define vISH_UART1_RTS_B 170 #define vCNV_BT_I2S_BCLK 171 #define vCNV_BT_I2S_WS_SYNC 172 +/* Group VGPIO 1 */ #define vCNV_BT_I2S_SDO 173 #define vCNV_BT_I2S_SDI 174 #define vSSP2_SCLK 175 @@ -310,35 +311,38 @@ #define GPD9 253 #define GPD10 254 #define GPD11 255 +#define SLP_LAN_B 256 +#define SLP_SUS_B 257 +#define WAKE_B 258 +#define DRAM_RESET_B 259 -#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) - +#define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1) /* Group AZA */ -#define HDA_BCLK 256 -#define HDA_RST_B 257 -#define HDA_SYNC 258 -#define HDA_SDO 259 -#define HDA_SDI0 260 -#define HDA_SDI1 261 -#define I2S1_SFRM 262 -#define I2S1_TXD 263 +#define HDA_BCLK 260 +#define HDA_RST_B 261 +#define HDA_SYNC 262 +#define HDA_SDO 263 +#define HDA_SDI0 264 +#define HDA_SDI1 265 +#define I2S1_SFRM 266 +#define I2S1_TXD 267 /* Group CPU */ -#define HDACPU_SDI 264 -#define HDACPU_SDO 265 -#define HDACPU_SCLK 266 -#define PM_SYNC 267 -#define PECI_IO 268 -#define CPUPWRGD 269 -#define THRMTRIP_B 270 -#define PLTRST_CPU_B 271 -#define PM_DOWN 272 -#define TRIGGER_IN 273 -#define TRIGGER_OUT 274 +#define HDACPU_SDI 268 +#define HDACPU_SDO 269 +#define HDACPU_SCLK 270 +#define PM_SYNC 271 +#define PECI_IO 272 +#define CPUPWRGD 273 +#define THRMTRIP_B 274 +#define PLTRST_CPU_B 275 +#define PM_DOWN 276 +#define TRIGGER_IN 277 +#define TRIGGER_OUT 278 #define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1) -#define TOTAL_PADS 275 +#define TOTAL_PADS 279 #define SD_PWR_EN_PIN GPP_A17 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index dc332d1fe4..9396c0bf2a 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -381,10 +381,14 @@ #define GPD9 308 #define GPD10 309 #define GPD11 310 +#define SLP_LAN_B 311 +#define SLP_SUS_B 312 +#define WAKE_B 313 +#define DRAM_RESET_B 314 -#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) +#define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1) -#define TOTAL_PADS (GPD11 + 1) +#define TOTAL_PADS (DRAM_RESET_B + 1) #define COMM_0 0 #define COMM_1 1 |