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| author | david <david_wu@quantatw.com> | 2016-01-08 20:49:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-09 14:07:21 +0100 |
| commit | 5d7df71cfe6c5a4c8615f33d194cb34947f53c05 (patch) | |
| tree | 5c63a3d5a05e9930b45c869521815cc60edc34ca | |
| parent | 825f937b81dda8cb0f73f27fb2146047d3db0f4e (diff) | |
| download | coreboot-5d7df71cfe6c5a4c8615f33d194cb34947f53c05.tar.xz | |
google/lars: Set I2C[4] port voltage to 1.8v
As the audio card needs 1.8V I2C operation. This patch adds
entry into devicetree.cb to set I2C port 4 operate at 1.8V.
TEST=Built & booted lars board. Verified that I2C
port 4 is operating at 1.8V level
Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c
Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321000
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/mainboard/google/lars/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index bc39f3e345..cf3649aa4d 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -146,6 +146,7 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) + register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ |